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參數(shù)資料
| 型號： | AM79C940VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 21/122頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940VCW |
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AMD
21
Am79C940
RXCRS Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance
RXCRS Output
RXCRS Output
RXCRS Input
RXCRS Input
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
DXCVR
Disable Transceiver (Output)
An output from the MACE device to indicate the network
port in use, as programmed by the ASEL bit or the
PORTSEL [1–0] bits. The output is provided to allow
power down of an external DC-to-DC converter, typi-
cally used to provide the voltage requirements for an ex-
ternal 10BASE2 transceiver.
When the Auto Select (ASEL) feature is enabled, the
state of the PORTSEL [1–0] bits is overridden, and the
network interface will be selected by the MACE device,
dependent only on the status of the 10BASE-T link. If the
link is active (
LNKST
pin driven LOW) the 10BASE-T
port will be used as the active network interface. If the
link is inactive (
LNKST
pin pulled HIGH) the AUI port will
be used as the active network interface. Auto Select will
continue to operate even when the
SLEEP
pin is as-
serted if the RWAKE bit has been set. The AWAKE bit
does not allow the Auto Select function, and only the re-
ceive section of 10BASE-T port will be active (DXCVR =
HIGH).
Active (HIGH) when either the 10BASE-T or DAI port is
selected. Inactive (LOW) when the AUI or GPSI port is
selected.
DXCVR Configuration—
SLEEP
Operation
SLEEP
Pin
RWAKE AWAKE
Bit
ASEL
Bit
LNKST
Pin
PORTSEL
[1–0] Bits
Interface
Description
Pin
Bit
Function
0
0
0
X
High
XX
Sleep
Mode
High
Impedance
High
Impedance
High
Impedance
High
Impedance
High
Impedance
High
Impedance
High
Impedance
HIGH
LOW
X
Impedance
LOW
0
1
0
0
00
AUI with EADI port
0
1
0
0
01
10BASE-T with EADI port
HIGH
0
1
0
0
10
Invalid
HIGH
0
1
0
0
11
Invalid
LOW
0
1
0
1
0X
AUI with EADI port
LOW
0
1
0
1
0X
10BASE-T with EADI port
HIGH
0
0
0
1
1
0
1
1
1
1
1
X
0X
0X
0X
AUI with EADI port
10BASE-T with EADI port
10BASE-T
LOW
HIGH
HIGH
Note:
RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and
ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). All bits must be programmed prior to the
assertion of the
SLEEP
pin.
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