參數(shù)資料
型號： AM79C940VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Media Access Controller for Ethernet (MACE)
中文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80
封裝： TQFP-80
文件頁數(shù)： 78/122頁
文件大?。?/td> 914K
代理商： AM79C940VCW
AMD
78
Am79C940
Programmer’s Register Model (continued)
Addr
Mnemonic
14
PLSCC
Physical Layer Signalling (PLS) Configuration Control
08
XMTSEL
06
PORTSEL [1:0]—Port Select (2 bits)
00
01
10
11
01
ENPLSIO Enable Status
15
PHYCC
Physical Layer (PHY) Configuration Control
80
LNKFL
40
DLNKTST Disable Link Test—Force 10BASE-T port into Link Pass
20
REVPOL
Reversed Polarity—Reports 10BASE-T receiver wiring error
10
DAPC
Disable Auto Polarity Correction—Detection remains active
08
LRT
Low Receive Threshold—Extended distance capability
04
ASEL
Auto Select—Select 10BASE-T port when active, otherwise AUI
02
RWAKE
Remote Wake—10BASE-T, AUI and EADI
features active during sleep
01
AWAKE
Auto Wake—10BASE-T receive and
LNKST
active during sleep
16
CHIPID
Chip Identification Register LSB—CHIPID [7:0]
17
CHIPID
Chip Identification Register MSB—CHIPID [15:8]
18
IAC
Internal Address Configuration
80
ADDRCHGAddress Change—Write to PHYADDR or LOGADDR after ENRCV
40
—
20
—
10
—
08
—
04
—
04
PHYADDR Reset Physical Address pointer
02
LOGADDR Reset Logical Address pointer
01
—
19
—
Reserved
Contents
R/W
Transmit Mode Select: 1
→
DO
±
= 1 during IDLE
AUI selected
10BASE-T selected
DAI port selected
GPSI selected
R/W
Link Fail—Reports 10BASE-T receive inactivity
RO
RO
R/W
as 0
R/W
R/W
R/W
as 0
R/W
as 0
RO
R/W
as 0
RO
RO
R/W
as 0
R/W
20
21
22
LADRF
PADR
—
Logical Address Filter—8 bytes—8 reads or writes—LS Byte first
Physical 6 bytes—6 reads or writes—LS Byte first
Reserved
23
—
Reserved
24
25
MPC
—
Missed Packet Counter—Number of receive packets missed
Reserved
26
27
28
RNTPC
RCVCC
—
Runt Packet Count—Number of runt packets addressed to this node
Receive Collision Count—Number of receive collision frames on network
Reserved
29
UTR
User Test Register
80
RTRE
40
RTRD
20
RPA
10
FCOLL
08
RCVFCSE Receive FCS Enable
06
LOOP
Loopback control (2 bits)
00
No loopback
01
External loopback
10
Internal loopback, excludes MENDEC
11
Internal loopback, includes MENDEC
01
—
Reserved Test Register Enable—must be 0
Reserved Test Register Disable
Runt Packet Accept
Force Collision
R/W
R/W
R/W
相關(guān)PDF資料
PDF描述
AM79C940 Media Access Controller for Ethernet (MACE)
AM79C940JCW Media Access Controller for Ethernet (MACE)
AM79C940KCW Media Access Controller for Ethernet (MACE)
AM79C960 PCnetTM-ISA Single-Chip Ethernet Controller
AM79C960KC PCnetTM-ISA Single-Chip Ethernet Controller
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