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參數(shù)資料
| 型號： | AM79C940VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 64/122頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940VCW |
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AMD
64
Am79C940
Bit 5
RDTREQ
Receive Data Transfer Request.
An internal indication of the
current request status of the Re-
ceive FIFO. RDTREQ is set
when the external
RDTREQ
sig-
nal is asserted.
Reserved. Read as zeroes.
Always write as zeroes.
Bit 4–0 RES
BIUConfigurationControl(BIUCC) (REGADDR11)
All bits within the BIU Configuration Control register will
be set to their default state upon a hardware or software
reset. Bit assignments are as follows:
RES
RES
RES
RES
BSWP XMTSP [1–0]
SWRST
Bit
Name
Description
Bit 7
RES
Reserved. Read as zero. Always
write as zero.
Byte Swap. The BSWP function
allows data to and from the
FIFOs to be orientated according
to little endian or big endian byte
ordering conventions. BSWP is
cleared by by activation of the
RESET
pin or SWRST bit, de-
faulting to Intel byte ordering.
Transmit Start Point. XMTSP
controls the point preamble
transmission commences in rela-
tion to the number of bytes writ-
ten to the XMTFIFO. When the
entire frame is in the XMTFIFO
(or the XMTFIFO becomes full
before
the
achieved), transmission of pre-
amble will start regardless of the
value in XMTSP (once the IPG
time has expired). XMTSP is
given a value of 10 (64 bytes) af-
ter hardware or software reset.
Regardless of XMTSP, the FIFO
will not internally over write its
data until at least 64 bytes, or the
entire frame, has been transmit-
ted onto the network. This en-
sures that for collisions within the
slot time window, transmit data
need not be re-written to the
XMTFIFO, and re-tries will be
handled autonomously by the
MACE device.
Transmit Start Point
Bit 6
BSWP
Bit 5-4
XMTSP
[1–0]
threshold
is
XMTSP [1–0]
Bytes
00
4
01
16
10
64
11
112
Bit 3-1
RES
Reserved. Read as zeroes.
Always write as zeroes.
Software Reset. When set, pro-
vides an equivalent of the hard-
ware
RESET
pin function. All
register bits will be set to their de-
fault values. The MACE device
will require re-initialization after
SWRST has been activated. The
MACE device will clear SWRST
during its internal reset se-
quence.
Bit 0
SWRST
FIFO Configuration Control
(FIFOCC)
All bits within the FIFO Configuration Control register
will be set to their default state upon a hardware or soft-
ware reset. Bit assignments are as follows:
(REG ADDR 12)
XMTFW[1–0] RCVFW [1–0] XMTFWU RCVFWU XMTBRST RCVBRST
Bit
Name
Description
Bit 7-6
XMTFW
[1–0]
Transmit
XMTFW
TDTREQ
is asserted in relation
to the number of write cycles to
the Transmit FIFO.
TDTREQ
will
be asserted at any time that the
number of write cycles specified
by XMTFW can be executed.
XMTFW is set to a value of 00 (8
cycles) after hardware or soft-
ware reset.
Transmit FIFO Watermarks
FIFO
controls
Watermark.
the
point
XMTFW [1–0]
Write Cycles
00
8
01
16
10
32
11
XX
The XMTFW value will only be
updated when the XMTFWU bit
is set.
To ensure that sufficient space is
present in the XMTFIFO to ac-
cept the specified number of
write cycles (including an End-
Of-Frame delimiter),
TDTREQ
may go inactive before the
XMTSP threshold is reached
when using the non burst mode
(XMTBRST = 0). The host must
be aware that despite
TDTREQ
going inactive, additional space
exists in the XMTFIFO, and the
data write must continue to en-
sure the XMTSP threshold is
achieved. No transmit activity will
commence until the XMTSP
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| AM79C940 | Media Access Controller for Ethernet (MACE) |
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| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
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| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
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