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| 型號(hào)： | AM79C940VCW |
| 廠(chǎng)商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁(yè)數(shù)： | 51/122頁(yè) |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940VCW |
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AMD
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Am79C940
current XMTFW value in the FIFO Configuration Control
register). If a whole frame does reside in the FIFO, the
read pointer will be moved to the start of the next frame
or free location in the FIFO, and the write pointer will be
unaffected.
TDTREQ
will not be re-asserted until the
Transmit Frame Status has been read.
After a RTRY error, all further packet transmission will
be suspended until the Transmit Frame Status is read,
regardless of whether additional packet data exists in
the FIFO to be transmitted. Receive FIFO read opera-
tions are not impaired.
Packets experiencing 16 unsuccessful attempt to trans-
mit will not be re-tried. Recovery from this condition
must be performed by upper layer software.
Abnormal network conditions include:
(a) Loss of carrier.
(b) Late collision.
(c) SQE Test Error.
These should not occur on a correctly configured 802.3
network, but will be reported if the network has been in-
correctly configured or a fault condition exists.
(a) A loss of carrier condition will be reported if the
MACE device cannot observe receive activity while it is
transmitting. After the MACE device initiates a transmis-
sion it will expect to see data looped-backon the receive
input path. This will internally generate a carrier sense,
indicating that the integrity of the data path to and from
the external MAU is intact, and that the MAU is operating
correctly.
When the AUI port is selected, if carrier sense does not
become active in response to the data transmission, or
becomes inactive before the end of transmission, the
loss of carrier (LCAR) error bit will be set in the Transmit
Frame Status (bit 7) after the packet has been transmit-
ted. The packet will not be re-tried on the basis of an
LCAR error.
When the 10BASE-T port is selected, LCAR will be re-
ported for every packet transmitted during the Link fail
condition.
When the GPSI port is selected, LCAR will be reported if
the RXCRS input pin fails to become active during a
transmission, or once active, goes inactive before the
end of transmission.
When the DAI port is selected, LCAR errors will not oc-
cur, since the MACE device will internally loop back the
transmit data path to the receiver. The loop back feature
must not be performed by the external transceiver when
the DAI port is used.
During internal loopback, LCAR will not be set, since the
MACE device has direct control of the transmit and re-
ceive path integrity. When in external loopback, LCAR
will operate normally according to the specific port which
has been selected.
(b) A late collision will be reported if a collision condition
exists or commences 64 byte times (512 bit times) after
the transmit process was initiated (first bit of preamble
commenced). The MACE device will abandon the trans-
mit process for the particular frame, complete transmis-
sion of the jam sequence (32-bit all zeroes pattern),
de-assert the
TDTREQ
pin, report the Late Collision
(LCOL) and Transmit Status Valid (XMTSV) in the
Transmit Frame Status, and set the XMTINT bit in the
Interrupt Register, causing activation of the external
INTR
pin providing the interrupt is unmasked.
Once the XMTINT condition has been externally recog-
nized, the Transmit Frame Counter (XMTFC) can be
read to determine whether the tail end of the frame that
suffers the LCOL error is still in the host memory (i.e.,
when XMTFC = 0). This XMTFC read should be re-
quested before the Transmit Frame Status read since
reading the XMTFS would cause the XMTFC to decre-
ment. If the tail end of the frame is indeed still in the host
memory, the host is responsible for ensuring that the tail
end of the frame does not get written into the FIFO and
does not get transmitted as a whole frame. It is recom-
mended that the host clear the tail end of the frame from
the host memory before requesting the XMTFS read so
that after the XMTFS read,when the MACE device re-
asserts
TDTREQ,
the tail end of the frame does not get
written into the FIFO. The Transmit Frame Status read
will indicate that the LCOL error occurred. The read op-
eration on the Transmit Frame Status will update the
FIFO read and write pointers. If no End-of-Frame write
(
EOF
pin assertion) had occurred during the FIFO write
sequence, the entire transmit path will be reset (which
will update the Transmit FIFO watermark with the cur-
rent XMTFW value in the FIFO Configuration Control
register). If a whole frame resides in the FIFO, the read
pointer will be moved to the start of the next frame or free
location in the FIFO, and the write pointer will be unaf-
fected.
TDTREQ
will not be re-asserted until the Trans-
mit Frame Status has been read.
After an LCOL error, all further packet transmission will
be suspended until the Transmit Frame Status is read,
regardless of whether additional packet data exists in
the FIFO to be transmitted. Receive FIFO operations
are unaffected.
Packets experiencing a late collision will not be re-tried.
Recovery from this condition must be performed by up-
per layer software.
(c) During the inter packet gap time following the com-
pletion of a transmitted message, the AUI CI
±
pair is
asserted by some transceivers as a self-test. When the
AUI port has been selected, the integral Manchester En-
coder/Decoder will expect the SQE Test Message
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