- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366550 > AM79C960KC (ADVANCED MICRO DEVICES INC) PCnetTM-ISA Single-Chip Ethernet Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C960KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | CARRIER RING, PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 42/127頁(yè) |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)當(dāng)前第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
P R E L I M I N A R Y
AMD
1-384
Am79C960
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the
phase-locked clock remains locked on the received sig-
nal. Individual bit cell phase corrections of the Voltage
Controlled Oscillator (VCO) are limited to 10% of the
phase difference between BCC and phase-locked
clock. Hence, input data jitter is reduced in ISRDCLK by
10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI
±
inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS deassert allows the last bit to
be strobed by ISRDCLK and transferred to the controller
section, but prevents any extra bit(s) at the end of
message.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI
±
/RXD
±
inputs. Input
error is less than
±
35 mV to minimize sensitivity to input
rise and fall time. ISRDCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following ISRDCLK. The data receiver also gener-
ates the signal used for phase detector comparison to
the internal MENDEC voltage controlled oscillator
(VCO).
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in the
pattern.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of “Jitter Han-
dling” is:
The peak deviation approaching or crossing 1/4
bit cell position from nominal input transition, for
which the MENDEC section will properly de-
code data.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which
connects the DTE to a MAU. The differential interface
provided by the PCnet-ISA controller is fully compliant
with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-ISA controller initiates a transmission, it
will expect to see data “l(fā)ooped-back” on the DI
±
pair
(when the AUI port is selected). This will internally
generate a “carrier sense”, indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted within sometime before end of trans-
mission. If “carrier sense” does not become active in
response to the data transmission, or becomes inactive
before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Descriptor
Ring (TMD3, bit 11) after the packet has been
transmitted.
Differential Input Terminations
The differential input for the Manchester data (DI
±
) is
externally terminated by two 40.2
±
1% resistors and
one optional common-mode bypass capacitor, as
shown in the Differential Input Termination diagram
below. The differential input impedance, Z
IDF
, and the
common-mode input impedance, Z
ICM
, are specified so
that the Ethernet specification for cable termination im-
pedance is met using standard 1% resistor terminators.
If SIP devices are used, 39
is the nearest usable
equivalent value. The CI
±
differential inputs are termi-
nated in exactly the same way as the DI
±
pair.
PCnet-ISA
DI+
DI-
40.2
40.2
0.01
μ
F
to 0.1
μ
F
AUI Isolation
Transformer
16907B-9
Differential Input Termination
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI
±
inputs. This
collision signal passes through an input stage which de-
tects signal levels and pulse duration. When the signal is
detected by the MENDEC it sets the ICLSN line HIGH.
The condition continues for approximately 1.5 bit times
after the last LOW-to-HIGH transition on CI
±
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C960KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C960KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。