參數(shù)資料
型號(hào): AM79C960KC
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: PCnetTM-ISA Single-Chip Ethernet Controller
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120
封裝: CARRIER RING, PLASTIC, QFP-120
文件頁(yè)數(shù): 55/127頁(yè)
文件大小: 814K
代理商: AM79C960KC
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
P R E L I M I N A R Y
AMD
1-397
Am79C960
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the packet (length field as defined in the
IEEE 802.3 standard). The length value contained in the
message is not used by the PCnet-ISA controller to
compute the actual number of pad bytes to be inserted.
The PCnet-ISA controller will append pad bytes de-
pendent on the actual number of bits transmitted onto
the network. Once the last data byte of the frame has
completed prior to appending the FCS, the PCnet-ISA
controller will check to ensure that 544 bits have been
transmitted. If not, pad bytes are added to extend the
frame size to this value, and the FCS is then added.
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble,
including FCS)
64 bytes
512 bits
Preamble/SFD size
8 bytes
64 bits
FCS size
4 bytes
32 bits
To be classed as a minimum-size frame at the receiver,
the transmitted frame must contain:
Preamble
+
(Min Frame Size + FCS) bits
At the point that FCS is to be appended, the transmitted
frame should contain:
Preamble
64
+
+
(Min Frame Size - FCS) bits
(512
-
32) bits
A minimum-length transmit frame from the PCnet-ISA
controller will, therefore, be 576 bits after the FCS is
appended.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit in
CSR15. When DXMTFCS = 0 the transmitter will gener-
ate and append the FCS to the transmitted frame. If the
automatic padding feature is invoked (APAD_XMT is
SET in CSR4), the FCS will be appended by the
PCnet-ISA controller regardless of the state of
DXMTFCS. Note that the calculated FCS is transmitted
most-significant bit first. The default value of DXMTFCS
is 0 after RESET.
Transmit Exception Conditions
Exception conditions for frame transmission fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to abnor-
mal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA controller are basically
collisions within the slot time with automatic retry. The
PCnet-ISA controller will ensure that collisions which
occur within 512 bit times from the start of transmission
(including preamble) will be automatically retried with no
host intervention. The transmit FIFO ensures this by
guaranteeing that data contained within the FIFO will
not be overwritten until at least 64 bytes (512 bits) of
data have been successfully transmitted onto the net-
work.
If 16 total attempts (initial attempt plus 15 retries) fail, the
PCnet-ISA controller sets the RTRY bit in the current
transmit TDTE in host memory (TMD2), gives up owner-
ship (sets the OWN bit to zero) for this packet, and
processes the next packet in the transmit ring for trans-
mission.
Abnormal network conditions include:
I
Loss of carrier
I
Late collision
I
SQE Test Error (does not apply to 10BASE-T port)
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be reset until the STP (the next frame)
is found.
Loss of Carrier
A loss of carrier condition will be reported if the
PCnet-ISA controller cannot observe receive activity
while it is transmitting on the AUI port. After the
PCnet-ISA controller initiates a transmission, it will
expect to see data “l(fā)ooped back” on the DI
±
pair. This
will internally generate a “carrier sense,” indicating that
the integrity of the data path to and from the MAU is in-
tact, and that the MAU is operating correctly. This
“carrier sense” signal must be asserted before the end
of the transmission. If “carrier sense” does not become
active in response to the data transmission, or becomes
inactive before the end of transmission, the loss of car-
rier (LCAR) error bit will be set in TMD2 after the frame
has been transmitted. The frame will not be re-tried on
the basis of an LCAR error. In 10BASE-T mode LCAR
will indicate that Jabber or Link Fail state has occurred.
Late Collision
A late collision will be reported if a collision condition oc-
curs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
The PCnet-ISA controller will abandon the transmit
process for the particular frame, set Late Collision
(LCOL) in the associated TMD3, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be re-tried. Recovery from this condition
must be performed by upper-layer software.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI
±
pair is
asserted by some transceivers as a self-test. The inte-
gral Manchester Encoder/Decoder will expect the SQE
Test Message (nominal 10 MHz sequence) to be re-
turned via the CI
±
pair within a 40 network bit time period
after DI
±
pair goes inactive. If the CI
±
inputs are not
asserted within the 40 network bit time period following
相關(guān)PDF資料
PDF描述
AM79C960KCW PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961A PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKIW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C960KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C960KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller
AM79C961 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961/AM79C961A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF)