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參數(shù)資料
| 型號(hào)： | AM79C960KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | CARRIER RING, PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 78/127頁(yè) |
| 文件大小： | 814K |
| 代理商： | AM79C960KC |
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P R E L I M I N A R Y
AMD
1-420
Am79C960
16907B-15
CRC
GEN
SEL
47
1
0
31
26
0
63
0
64
MUX
MATCH = 1:
Packet Accepted
MATCH = 0:
Packet Rejected
1
6
MATCH
Logical
Address
Filter
(LADRF)
Received Message
Destination Address
32-Bit Resultant CRC
Address Match Logic
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility to
determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all zeroes and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
1)
If the Disable Broadcast Bit is cleared, the
broadcast address is accepted.
2)
If the Disable Broadcast Bit is set and promiscuous
mode is enabled, the broadcast address is
accepted.
3)
If the Disable Broadcast Bit is set and promiscous
mode is disabled, the broadcast address is rejected.
If external loopback is used, the FCS logic must be allo-
cated to the receiver (by setting the DXMTFCS bit in
CSR15, and clearing the ADD_FCS bit in TMD1) when
using multicast addressing.
PADR
This 48-bit value represents the unique node address
assigned by the IEEE and used for internal address
comparison. PADR[0] is the first address bit transmitted
on the wire, and must be zero. The six-byte nomencla-
ture used by the IEEE maps to the PCnet-ISA controller
PADR register as follows: the first byte comprises
PADR[7:0], with PADR[0] being the least significant bit
of the byte. The second IEEE byte maps to PADR[15:8],
again from LSbit to MSbit, and so on. The sixth byte
maps to PADR[47:40], the LSbit being PADR[40].
MODE
The mode register in the initialization block is copied into
CSR15 and interpreted according to the description of
CSR15.
Receive Descriptors
The Receive Descriptor Ring Entries (RDREs) are com-
posed of 4 receive message fields (RMD0-3). Together
they contain the following information:
I
The address of the actual message data buffer in
user (host) memory.
I
The length of that message buffer.
I
Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[15:0]) are collectively termed the STATUS
of the receive descriptor.
RMD0
Holds LADR [15:0]. This is combined with HADR [7:0] in
RMD1 to form the 24-bit address of the buffer pointed to
by this descriptor table entry. There are no restrictions
on buffer byte alignment or length.
RMD1
Bit
Name
Description
15
OWN
This bit indicates that the de-
scriptor entry is owned by the
host
(OWN=0)
PCnet-ISA controller (OWN=1).
The PCnet-ISA controller clears
the OWN bit after filling the buffer
pointed to by the descriptor entry.
The host sets the OWN bit after
emptying the buffer. Once the
PCnet-ISA controller or host has
relinquished ownership of a
or
by
the
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| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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| AM79C960KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
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