參數(shù)資料
型號： AM79C960KC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120
封裝： CARRIER RING, PLASTIC, QFP-120
文件頁數(shù)： 62/127頁
文件大小： 814K
代理商： AM79C960KC
P R E L I M I N A R Y
AMD
1-404
Am79C960
4
DXMT2PD
Disable Transmit Two Part
Deferral. If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
DXMT2PD is cleared by RESET
and is not affected by STOP.
Enable
Modified
Algorithm. If EMBA is set, a modi-
fied
back-off
implemented.
Read/Write accessible. EMBA is
cleared by RESET and is not af-
fected by STOP.
Reserved locations. Written as
zero and read as undefined.
3
EMBA
Back-off
algorithm
is
2-0
RES
CSR4: Test and Features Control
Bit
Name
Description
15
ENTST
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
register test functions are en-
abled. In order to set ENTST, it
must be written with a “1” during
the first write access to CSR4
after RESET. Once a “0” is writ-
ten to this bit location, ENTST
cannot be set until after the
PCnet-ISA controller is reset.
ENTST is cleared by RESET.
When DMAPLUS = “1” , the burst
transaction counter in CSR80 is
disabled. If DMAPLUS = “0”, the
burst transaction counter is
enabled.
DMA-PLUS
is
RESET.
Timer Enable Register. If TIMER
is set, the Bus Timer Register,
CSR82, is enabled. If TIMER is
set, CSR82 must be written with
a value. If TIMER is cleared, the
Bus Timer Register is disabled.
TIMER is cleared by RESET.
Disable Transmit Polling. If
DPOLL is set, the Buffer Man-
agement
Unit
transmit polling. Likewise, if
DPOLL is cleared, automatic
transmit polling is enabled. If
DPOLL is set, TDMD bit in CSR0
must be periodically set in order
to initiate a manual poll of a trans-
mit descriptor. Transmit descrip-
tor polling will not take place if
TXON is reset.
14
DMAPLUS
cleared
by
13
TIMER
12
DPOLL
will
disable
DPOLL is cleared by RESET.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the en-
tire frame (including pad) and
appended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15.3).
APAD_ XMT is reset by activa-
tion of the RESET pin.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
ASTRP_ RCV is reset by activa-
tion of the RESET pin.
Missed Frame Counter Overflow
Interrupt.
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a “1” to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a “0”
has no effect.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will not
set INTR in CSR0.
MFCOM is set by Reset and is
not affected by STOP.
Reserved locations. Read and
written as zero.
Receive Collision Counter Over-
flow.
This bit indicates the Receive
Collision Counter (CSR114) has
overflowed. It can be cleared by
writing a 1 to this bit. Also cleared
by RESET or setting the STOP
bit. Writing a 0 has no effect.
Receive Collision Counter Over-
flow Mask.
If RCVCCOM is set, RCVCCO
will not set INTR in CSR0.
RCVCCOM is set by RESET and
is not affected by STOP.
Transmit Start status is set when-
ever PCnet-ISA controller begins
trans- mission of a frame.
When TXSTRT is set, IRQ is as-
serted if IENA = 1 and the mask
bit TXSTRTM (CSR4.2) is clear.
11
APAD_XMT
10 ASTRP_RCV
9
MFCO
8
MFCOM
7-6
RES
5
RCVCCO
4
RCVCCOM
3
TXSTRT
相關(guān)PDF資料
PDF描述
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