參數(shù)資料
型號： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 100/206頁
文件大?。?/td> 1507K
代理商： AM79C961AVIW
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁當(dāng)前第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁
100
Am79C961A
back-off
implemented as described in the
Media
Access
section.
Read/Write accessible. EMBA is
cleared by RESET and is not
affected by STOP.
Reserved locations. Written as
zero and read as undefined.
algorithm
is
Management
2-0
RES
CSR4: Test and Features Control
Bit
Name
Description
15
ENTST
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
register
test
enabled. In order to set ENTST, it
must be written with a
“
1" during
the first write access to CSR4
after RESET. Once a
“
0" is writ-
ten to this bit location, ENTST
cannot be set until after the PC-
net-ISA II controller is reset.
ENTST is cleared by RESET.
When DMAPLUS =
“
1", the burst
transaction counter in CSR80 is
disabled. If DMAPLUS =
“
0", the
burst transaction counter is
enabled.
Caution
: When using DMAPLUS
AND/OR TIMER bits in a PC
environment, care must be taken
not to hold the bus for more than
the required refresh time.
DMAPLUS is cleared by RESET.
Timer Enable Register. If TIMER
is set, the Bus Activity Timer reg-
ister (CSR82) is enabled and the
PCnet-ISA II may perform any
combination of accesses (buffer
reads, buffer writes, descriptor
reads, and descriptor writes)
during a single bus mastership
period. The bus is held until
either the Bus Activity Timer
expires or there are no further
pending operations to be per-
formed. The PCnet-ISA II deter-
mines whether there are further
pending bus operations by wait-
ing approximately 1
μ
s after the
completion of every bus opera-
tion (e.g. a descriptor or FIFO
access). If, during the 1
μ
s
period, no further bus operations
are requested by the internal
Buffer Management Unit, the
PCnet-ISA II determines that
functions
are
14
DMAPLUS
13
TIMER
there are no further pending
operations and gives up bus
ownership.
If TIMER is cleared, the Bus
Activity Timer register is dis-
abled and the PCnet-ISA II per-
forms only one type of access
(descriptor
read,
write, buffer read, or buffer
write) and buffer accesses are
performed
to
ascending addresses during
each bus mastership period.
TIMER is cleared by RESET.
Disable Transmit Polling. If
DPOLL is set, the Buffer Man-
agement Unit will disable trans-
mit polling. Likewise, if DPOLL is
cleared, automatic transmit poll-
ing is enabled. If DPOLL is set,
TDMD bit in CSR0 must be peri-
odically set in order to initiate a
manual poll of a transmit
descriptor. Transmit descriptor
polling will not take place if
TXON is reset.
DPOLL is cleared by RESET.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the en-
tire frame (including pad) and
appended after the pad field.
APAD_XMT will override the
programming of the DXMTFCS
bit (CSR15.3).
APAD_ XMT is reset by activa-
tion of the RESET pin.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames
and not placed in the FIFO.
ASTRP_ RCV is reset by activa-
tion of the RESET pin.
Missed Frame Counter Overflow
Interrupt.
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a
“
1" to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a
“
0" has no effect.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will not
set INTR in CSR0.
descriptor
adjacent
12
DPOLL
11
APAD_XMT
10 ASTRP_RCV
9
MFCO
8
MFCOM
相關(guān)PDF資料
PDF描述
Am79C965A PCnet?-32 Single-Chip 32-Bit Ethernet Controller
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C961KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C965A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*