102
Am79C961A
Read/Write accessible always.
SPND is cleared by asserting
the RESET pin, reading the
RESET register, or setting the
STOP bit
Magic Packet Mode.
Setting this bit is a prerequisite
for entering the Magic Packet
mode. It also redefines the
SLEEP pin to be a Magic Packet
enable pin. Read/Write accessi-
ble always. It is cleared by as-
serting the RESET pin, or read-
ing the RESET register.
Magic Packet Enable.
This bit when set, will force the
PCnet-ISA II into the Magic
Packet mode. Read/Write ac-
cessible always. It is cleared by
asserting the RESET pin or
reading the RESET register.
Magic Packet Interrupt Enable.
Acts as an unmask bit for the
MP_INT (CSR5, bit 4). Read/
Write accessible always. It is
cleared by asserting the RESET
pin or reading the RESET regis-
ter, or setting the STOP bit.
Magic Packet Receive Interrupt.
Will be set when a Magic Packet
has been received. Writing a
“
one
”
will clear this bit. It is
cleared by asserting the RESET
pin, or reading the RESET regis-
ter.
1
MP_MODE
2
MP_ENBL
3
MP_I_ENBL
4
MP_INT
CSR6: RCV/XMT Descriptor Table Length
Bit
Name
Description
15-12
TLEN
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-ISA II controller ini-
tialization. This field is written
during the PCnet-ISA II controller
initialization routine.
Read accessible only when STOP
or SPND bits are set. Write oper-
ations have no effect and should
not be performed. TLEN is only
defined after initialization.
Contains a copy of the receive
encoded ring length (RLEN)
read from the initialization
block during PCnet-ISA II con-
troller initialization. This field is
written during the PCnet-ISA II
controller initialization routine.
11-8
RLEN
Read accessible only when
STOP or SPND bits are set. Write
operations have no effect and
should not be performed. RLEN is
only defined after initialization.
Reserved locations. Read as
zero. Write operations should
not be performed.
7-0
RES
CSR8: Logical Address Filter, LADRF[15:0]
Bit
Name
Description
15-0 LADRF[15:0]
Logical Address Filter, LADRF
[15:0]. Undefined until initialized
either automatically by loading
the initialization block or directly
by an I/O write to this register.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR9: Logical Address Filter, LADRF[31:16]
Bit
Name
Description
15-0 LADRF[31:16] Logical
Address
Filter,
LADRF[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR10: Logical Address Filter, LADRF[47:32]
Bit
Name
Description
15-0 LADRF[47:32] Logical
Address
Filter,
LADRF[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR11: Logical Address Filter, LADRF[63:48]
Bit
Name
Description
15-0 LADRF[63:48] Logical
Address
Filter,
LADRF[63:48]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.