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參數(shù)資料
| 型號： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 18/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVIW |
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18
Am79C961A
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IEEE P996 Terminology
Alternate Master
: Any device that can take control of
the bus through assertion of the MASTER signal. It has
the ability to generate addresses and bus control sig-
nals in order to perform bus operations. All Alternate
Masters must be 16 bit devices and drive
SBHE
.
Bus Ownership
: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
Current Master
: The Permanent Master, Temporary
Master or Alternate Master which currently has owner-
ship of the bus.
Permanent Master
: Each P996 bus will have a device
known as the Permanent Master that provides certain
signals and bus control functions as described in Sec-
tion 3.5 (of the IEEE P996 spec.),
“
Permanent Master
”
.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
Temporary Master
: A device that is capable of gener-
ating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes
during bus transfer. Addresses are generated by the
DMA device on the Permanent Master.
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus performs
an I/O access to the device.
BALE
Used to latch the LA20
–
23 address lines.
DACK 3, 5-7
DMA Acknowledge
Asserted LOW when the Permanent Master acknowl-
edges a DMA request. When DACK is asserted the
PCnet-ISA II
controller becomes the Current Master by
asserting the MASTER signal.
DRQ 3, 5-7
DMA Request
When the PCnet-ISA II controller needs to perform a
DMA transfer, it asserts DRQ. The Permanent Master
acknowledges DRQ with the assertion of DACK. When
the PCnet-ISA II does not need the bus it desserts
DRQ. The PCnet-ISA II provides for fair bus bandwidth
sharing between two bus mastering devices on the ISA
bus through an adaptive delay which is inserted
Input
Input
Input/Output
between back-to-back DMA requests. See the
Back-to-Back DMA Requests section for details.
Because of the operation of the Plug and Play regis-
ters, the DMA Channels on the PCnet-ISA II must be
attached to the specific DRQ and DACK signals on the
PC/AT bus as indicated by the pin names.
IOCHRDY
I/O Channel Ready
When the PCnet-ISA II controller is being accessed,
IOCHRDY HIGH indicates that valid data exists on the
data bus for reads and that data has been latched for
writes. When the PCnet-ISA II controller is the Current
Master on the ISA bus, it extends the bus cycle as long
as IOCHRDY is LOW.
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA II controller will drive the IOCS16 pin LOW
to indicate that the chip supports a 16-bit operation at
this address. (If the motherboard does not receive this
signal, then the motherboard will convert a 16-bit
access to two 8-bit accesses).
Input/Output
Output
The PCnet-ISA II controller follows the IEEE P996 spec-
ification that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depen-
dency on IOR, or IOW; however, some PC/AT clone sys-
tems are not compatible with this approach. For this
reason, the PCnet-ISA II controller is recommended to
be configured to run 8-bit I/O on all machines. Since data
is moved by memory cycles there is virtually no perfor-
mance loss incurred by running 8-bit I/O and compatibil-
ity problems are virtually eliminated. The PCnet-ISA II
controller can be configured to run 8-bit-only I/O by
clearing Bit 0 in Plug and Play register F0.
IOR
I/O Read
IOR is driven LOW by the host to indicate that an Input/
Output Read operation is taking place. IOR is only valid
if the AEN signal is LOW and the external address
matches the PCnet-ISA II controller
’
s predefined I/O
address location. If valid, IOR indicates that a slave
read operation is to be performed.
IOW
I/O Write
IOW is driven LOW by the host to indicate that an Input/
Output Write operation is taking place. IOW is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA II controller
’
s predefined I/O address
location. If valid, IOW indicates that a slave write oper-
ation is to be performed.
Input
Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
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