參數(shù)資料
型號(hào)： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 129/206頁(yè)
文件大小： 1507K
代理商： AM79C961AVIW
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Am79C961A
129
SYSTEM APPLICATION
ISA Bus Interface
Compatibility Considerations
Although 8 MHz is now widely accepted as the standard
speed at which to run the ISA bus, many machines have
been built which operate at higher speeds with non-stan-
dard timing. Some machines do not correctly support
16-bit I/O operations with wait states. Although the PC-
net-ISA II controller is quite fast, some operations still re-
quire an occasional wait state. The PCnet-ISA II
controller moves data through memory accesses, there-
fore, I/O operations do not affect performance. By con-
figuring the PCnet-ISA II controller as an 8-bit I/O device,
compatibility with PC/AT-class machines is obtained at
virtually no cost in performance. To treat the PCnet-ISA
II controller as an 8-bit software resource (for non-ISA
applications), the even-byte must be accessed first,
followed by an odd-byte access.
Memory cycle timing is an area where some tradeoffs
may be necessary. Any slow down in a memory cycle
translates directly into lower bandwidth. The PC-
net-ISA II controller starts out with much higher band-
width than most slave type controllers and should
continue to be superior even if an extra 50 or 100 ns
are added to memory cycles.
The memory cycle active time is tunable in 50 ns incre-
ments with a default of 250 ns. The memory cycle idle
time defaults to 200 ns and can be reprogrammed to
100 ns. See register description for ISACS42. Most
machines should not need tuning.
The PCnet-ISA II controller is compatible with NE2100
and NE1500T software drivers. All the resources such
as address PROM, boot PROM, RAP, and RDP are in
the same location with the same semantics. An addi-
tional set of registers (ISA CSR) is available to config-
ure on board resources such as ISA bus timing and
LED operation. However, loopback frames for the PC-
net-ISA II controller must contain more than 64 bytes of
data if the Runt Packet Accept feature is not enabled;
this size limitation does not apply to LANCE (Am7990)
based boards such as the NE2100 and NE1500T.
Bus Master
Bus Master mode is the preferred mode for client appli-
cations on PC/AT or similar machines supporting 16-bit
DMA with its unsurpassed combination of high perfor-
mance and low cost.
Shared Memory
The shared memory mode is recommended for file
servers or other applications where there is very high,
average or peak latency.
The address compare circuit has the following func-
tions. It receives the 7 LA signals, generates
MEMCS16, and compares them to the desired shared
memory and boot PROM addresses. The logic latches
the address compare result when BALE goes inactive
and uses the appropriate SA signals to generate
SMAM and BPAM.
All these functions can be performed in one PAL
device. To operate in an 8-bit PC/XT environment, the
LA signals should have weak pull-down resistors con-
nected to them to present a logic 0 level when not
driven.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C961KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C965A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller
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