Am79C973/Am79C975
295
P R E L I M I N A R Y
BCR29
Expansion Port Address Upper
(Used for Flash/EPROM
Accesses) . . . . . . . . . . . . . . . . . . . .183
BCR30
Expansion Bus Data Port Register . . . .184
BCR31
Software Timer Register . . . . . . . . . . .184
BCR32 PHY Control and Status Register .185
BCR33
PHY Address Register . . . . . . . . . . . . .187
BCR34
PHY Management Data Register . . . . .187
BCR35
PCI Vendor ID Register . . . . . . . . . . . .187
BCR36
PCI Power Management Capabilities
(PMC) Alias Register . . . . . . . . . . .188
BCR37
PCI DATA Register Zero (DATA0)
Alias Register . . . . . . . . . . . . . . . . .188
BCR38
PCI DATA Register One (DATA1)
Alias Register . . . . . . . . . . . . . . . . .188
BCR39
PCI DATA Register Two (DATA2)
Alias Register . . . . . . . . . . . . . . . . .189
PCI DATA Register Zero (DATA2)
Alias Register . . . . . . . . . . . . . . . . .189
BCR4
LED 0 Status . . . . . . . . . . . . . . . . . . . .164
BCR40
PCI Data Register Three (DATA3)
Alias Register . . . . . . . . . . . . . . . . .189
BCR41
PCI DATA Register Four (DATA4)
Alias Register . . . . . . . . . . . . . . . . .189
BCR42
PCI DATA Register Five (DATA5)
Alias Register . . . . . . . . . . . . . . . . .190
BCR43
PCI DATA Register Six (DATA6)
Alias Register . . . . . . . . . . . . . . . . .190
BCR44
PCI DATA Register Seven (DATA7)
Alias Register . . . . . . . . . . . . . . . . .191
BCR45
OnNow Pattern Matching
Register #1 . . . . . . . . . . . . . . . . . . .191
BCR46
OnNow Pattern Matching
Register #2 . . . . . . . . . . . . . . . . . . .191
BCR47
OnNow Pattern Matching
Register #3 . . . . . . . . . . . . . . . . . . .192
BCR5
LED1 Status . . . . . . . . . . . . . . . . . . . . .166
BCR6
LED2 Status . . . . . . . . . . . . . . . . . . . . .168
BCR7
LED3 Status . . . . . . . . . . . . . . . . . . . . .169
BCR9
Full-Duplex Control . . . . . . . . . . . . . . .171
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . .4
Block Diagram Low Latency
Receive Configuration . . . . . . . . . . . . . . .97
Block Diagram No SRAM
Configuration . . . . . . . . . . . . . . . . . . . . . .97
Board Interface . . . . . . . . . . . . . . . . . . . . . .31
Boundary Scan Circuit . . . . . . . . . . . . . . . .106
Boundary Scan Register . . . . . . . . . . . . . .106
BSR Mode Of Operation . . . . . . . . . . . . . .107
Buffer Management . . . . . . . . . . . . . . . . . . .64
Buffer Management Unit . . . . . . . . . . . . . . .63
Buffer Size Tuning . . . . . . . . . . . . . . . . . .290
Burst FIFO DMA Transfers . . . . . . . . . . . . .62
Burst Write Transfer . . . . . . . . . . . . . . . . . .50
Bus Acquisition . . . . . . . . . . . . . . . . . . .46, 47
Bus Command and Byte Enables . . . . . . . .29
Bus Configuration Registers . . . . . . .157, 218
Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Bus Master DMA Transfers . . . . . . . . . . . . .47
Bus Request . . . . . . . . . . . . . . . . . . . . . . . . .31
C
Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . .35
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
CLK Waveform for 3.3 V Signaling . . . . .236
CLK Waveform for 5 V Signaling . . . . . .236
CLK_FAC Values . . . . . . . . . . . . . . . . . . .183
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Interface . . . . . . . . . . . . . . . . . . . . . . .37
Clock Timing . . . . . . . . . . . . . . .227, 231, 266
COL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Collision Detect Function . . . . . . . . . . . . . .87
Collision Handling . . . . . . . . . . . . . . . . . . . .73