參數(shù)資料
型號(hào)： AM79C973
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù)： 79/304頁(yè)
文件大小： 2092K
代理商： AM79C973
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Am79C973/Am79C975
79
P R E L I M I N A R Y
I
PHY Control Register (ANR0) bit 8 is set to 1 if Auto-
Negotiation is disabled.
Full-Duplex Link Status LED Support
The Am79C973/Am79C975 controller provides bits in
each of the LED Status registers (BCR4, BCR5, BCR6,
BCR7) to display the Full-Duplex Link Status. If the
FDLSE bit (bit 8) is set, a value of 1 will be sent to the
associated LEDOUT bit when in Full-Duplex.
10/100 PHY Unit Overview
The 10/100 PHY unit implements the complete physi-
cal layer for 10BASE-T and the Physical Coding Sub-
layer (PCS), Physical Medium Attachment (PMA), and
Physical Medium Dependent (PMD) functionality for
100BASE-TX. The 10/100 PHY implements Auto-
Negotiation allowing two devices connected across a
link segment to take maximum advantage of their capa-
bilities. Auto-Negotiation is performed using a modified
10BASE-T link integrity test pulse sequence as defined
in the IEEE 802.3u specification.
The internal 10/100 PHY consists of the following
functional blocks:
I
100BASE-X Block including:
—
Transmit and Receive State Machines
—
4B/5B Encoder and Decoder
—
Stream Cipher Scrambler and Descrambler
—
Link Monitor State Machine
—
Far End Fault Indication (FEFI) State Machine
—
MLT-3 Encoder
—
MLT-3 Decoder with adaptive equalization
I
10BASE-T Block including:
—
Manchester Encoder/Decoder
—
Collision Detection
—
Jabber
—
Receive Polarity Detect
—
Waveshaping and Filtering
I
Auto-Negotiation
I
Physical Data Transceiver (PDX)
I
PHY Control and Management
100BASE-TX Physical Layer
The functions performed by the device include encod-
ing of 4-bit data (4B/5B), decoding of received code
groups (5B/4B), generating carrier sense and collision
detect indications, serialization of code groups for
transmission, de-serialization of serial data from recep-
tion, mapping of transmit, receive, carrier sense, and
collision at the PHY/MAC interface, and recovery of
clock from the incoming data stream. It offers stream ci-
pher scrambling and descrambling capability for
100BASE-TX applications.
In the transmit data path for 100 Mbps, the 10/100 PHY
receives 4-bit (nibble) wide data across the internal MII
at 25 million nibbles per second. For 100BASE-TX ap-
plications, it encodes and scrambles the data, serial-
izes it, and transmits an MLT-3 data stream to the
media via an isolation transformer.
The 10/100 PHY receives an MLT-3 data stream from
the network for 100BASE-TX. It then recovers the clock
from the data stream, de-serializes the data stream,
and descrambles/decodes the data stream (5B/4B) be-
fore presenting it to the internal MII interface.
100BASE-FX (Fiber Interface)
The Am79C973/Am79C975 device supports a
Pseudo-ECL (PECL) interface for Fiber applications.
The mode is enabled when BCR2 bit 14
(DISSCR_SFEX) is set to 1 and the Signal Detect pins
SDI± are connected to the optical transceiver.
For 100BASE-FX receive operation, the PHY unit re-
ceives a PECL data stream from the optical transceiver
and decodes the data stream. For transmit operation,
the PHY unit encodes and serializes the data and
transmits a pseudo-ECL data stream to the fiber optic
transceiver. See Figure 35.
The Fiber Interface (100BASE-FX) does not support
Auto-Negotiation, 10 BASE-FL, and data scrambling.
When the device is set to operate in PECL mode, the
100BASE-TX operation will be disabled.
10BASE-T Physical Layer
The 10/100 PHY incorporates 10BASE-T physical
layer functions, including both clock recovery (ENDEC)
and transceiver functions. Data transmission over the
10BASE-T medium requires an integrated 10BASE-T
MAU. The transceiver will meet the electrical require-
ments for 10BASE-T as specified in IEEE 802.3i. The
transmit signal is filtered on the transceiver to reduce
harmonic content per IEEE 802.3i. Since filtering is
performed in silicon, external filtering modules are not
needed. The 10/100 PHY receives 10-Mbps data from
the MAC across the internal MII at 2.5 million nibbles
per second for 10BASE-T. It then Manchester encodes
the data before transmission to the network.
The RX+ pins are differential twisted-pair receivers.
When properly terminated, each receiver will meet the
electrical requirements for 10BASE-T as specified in
IEEE 802.3i. Each receiver has internal filtering and
does not require external filter modules. The 10/100
PHY receives a Manchester coded 10BASE-T data
stream from the medium. It then recovers the clock and
decodes the data.
相關(guān)PDF資料
PDF描述
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C973/75 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF)
AM79C973/AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973AVC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C973AVC\W 制造商:Advanced Micro Devices 功能描述:
AM79C973BKC 制造商:Advanced Micro Devices 功能描述:79C973BKC
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