參數(shù)資料
型號(hào)： AM79C973
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù)： 40/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C973
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40
Am79C973/Am79C975
P R E L I M I N A R Y
DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
to the PCI configuration space, the Control and Status
Registers (CSR), the Bus Configuration Registers
(BCR), the Address PROM (APROM) locations, and
the Expansion ROM. Table 3 shows the response of
the Am79C973/Am79C975 controllers to each of the
PCI commands in slave mode.
Table 3. Slave Commands
Slave Configuration Transfers
The host can access the Am79C973/Am79C975 PCI
configuration space with a configuration read or write
command. The Am79C973/Am79C975 controllers will
assert DEVSEL during the address phase when IDSEL
is asserted, AD[1:0] are both 0, and the access is a
configuration cycle. AD[7:2] select the DWord location
in the configuration space. The Am79C973/Am79C975
controllers ignore AD[10:8], because it is a single func-
tion device. AD[31:11] are don
’
t care.
The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, and 32-bit trans-
fers are supported. DEVSEL is asserted two clock cy-
cles after the host has asserted FRAME. All
configuration cycles are of fixed length. The
Am79C973/Am79C975 controllers will assert TRDY on
the third clock of the data phase.
The Am79C973/Am79C975 controllers do not support
burst transfers for access to configuration space. When
the host keeps FRAME asserted for a second data
phase, the Am79C973/Am79C975 controllers will dis-
connect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C973/Am79C975 controllers will terminate the
access on the PCI bus with a disconnect/retry re-
sponse.
The Am79C973/Am79C975 controllers support fast
back-to-back transactions to different targets. This is in-
dicated by the Fast Back-To-Back Capable bit (PCI Sta-
tus register, bit 7), which is hardwired to 1. The
Am79C973/Am79C975 controllers are capable of de-
tecting a configuration cycle even when its address
phase immediately follows the data phase of a transac-
tion to a different target without any idle state in-be-
tween. There will be no contention on the DEVSEL,
TRDY, and STOP signals, since the Am79C973/
Am79C975 controllers assert DEVSEL on the second
clock after FRAME is asserted (medium timing).
Slave I/O Transfers
After the Am79C973/Am79C975 controllers are config-
ured as an I/O device by setting IOEN (for regular I/O
mode) or MEMEN (for memory mapped I/O mode) in
the PCI Command register, it starts monitoring the PCI
bus for access to its CSR, BCR, or APROM locations.
If configured for regular I/O mode, the Am79C973/
Am79C975 controllers will look for an address that falls
within its 32 bytes of I/O address space (starting from
the I/O base address). The Am79C973/Am79C975
controllers assert DEVSEL if it detects an address
match and the access is an I/O cycle. If configured for
memory mapped I/O mode, the Am79C973/
Am79C975 controllers will look for an address that falls
within its 32 bytes of memory address space (starting
from the memory mapped I/O base address). The
C[3:0]
Command
Use
0000
Interrupt
Acknowledge
Not used
0001
Special Cycle
Not used
0010
I/O Read
Read of CSR, BCR, APROM,
and Reset registers
0011
I/O Write
Write to CSR, BCR, and
APROM
0100
Reserved
0101
Reserved
0110
Memory Read
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers
Read of the Expansion Bus
0111
Memory Write
Memory mapped I/O write of
CSR, BCR, and APROM
1000
Reserved
1001
Reserved
1010
Configuration
Read
Read of the Configuration
Space
1011
Configuration
Write
Write to the Configuration
Space
1100
Memory Read
Multiple
Aliased to Memory Read
1101
Dual Address
Cycle
Not used
1110
Memory Read
Line
Aliased to Memory Read
1111
Memory Write
Invalidate
Aliased to Memory Write
AD31
AD11
AD10
AD8
AD7
AD2
DWord
index
AD1
AD0
Don
’
t care
Don
’
t care
0
0
相關(guān)PDF資料
PDF描述
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
相關(guān)代理商/技術(shù)參數(shù)
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AM79C973/AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973AVC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C973AVC\W 制造商:Advanced Micro Devices 功能描述:
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