- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C973 (Advanced Micro Devices, Inc.) PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY PDF資料下載
參數(shù)資料
| 型號： | AM79C973 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁數(shù)： | 47/304頁 |
| 文件大小： | 2092K |
| 代理商： | AM79C973 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁
Am79C973/Am79C975
47
P R E L I M I N A R Y
starts driving AD[31:0] and C/BE[3:0] on clock 5.
FRAME is asserted at clock 5 indicating a valid ad-
dress and command on AD[31:0] and C/BE[3:0].
Figure 11. Bus Acquisition
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to 0, REQ is deasserted at the same time as
FRAME is asserted. (The Am79C973/Am79C975 con-
troller never performs more than one burst transaction
within a single bus mastership period.) If EXTREQ is
set to 1, the Am79C973/Am79C975 controller does not
deassert REQ until it starts the last data phase of the
transaction. Once asserted, REQ remains active until
GNT has become active and independent of subse-
quent setting of STOP (CSR0, bit 2) or SPND (CSR5,
bit 0). The assertion of H_RESET or S_RESET, how-
ever, will cause REQ to go inactive immediately.
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C973/Am79C975 controller uses non-burst as
well as burst cycles for read and write access to the
main memory.
Basic Non-Burst Read Transfer
By default, the Am79C973/Am79C975 controller uses
non-burst cycles in all bus master read operations. All
Am79C973/Am79C975 controller non-burst read ac-
cesses are of the PCI command type Memory Read
(type 6). Note that during a non-burst read operation,
all byte lanes will always be active. The Am79C973/
Am79C975 controller will internally discard unneeded
bytes.
The Am79C973/Am79C975 controller typically per-
forms more than one non-burst read transaction within
a single bus mastership period. FRAME is dropped be-
tween consecutive non-burst read cycles. REQ how-
ever stays asserted until FRAME is asserted for the last
transaction. The Am79C973/Am79C975 controller
supports zero wait state read cycles. It asserts IRDY
immediately after the address phase and at the same
time starts sampling DEVSEL. Figure 12 shows two
non-burst read transactions. The first transaction has
zero wait states. In the second transaction, the target
extends the cycle by asserting TRDY one clock later.
Basic Burst Read Transfer
The Am79C973/Am79C975 controller supports burst
mode for all bus master read operations. The burst
mode must be enabled by setting BREADE (BCR18, bit
6). To allow burst transfers in descriptor read opera-
tions, the Am79C973/Am79C975 controller must also
be programmed to use SWSTYLE 3 (BCR20, bits 7-0).
All burst read accesses to the initialization block and
descriptor ring are of the PCI command type Memory
Read (type 6). Burst read accesses to the transmit
buffer typically are longer than two data phases. When
MEMCMD (BCR18, bit 9) is cleared to 0, all burst read
accesses to the transmit buffer are of the PCI com-
mand type Memory Read Line (type 14). When MEM-
CMD (BCR18, bit 9) is set to1, all burst read accesses
to the transmit buffer are of the PCI command type
Memory Read Multiple (type 12). AD[1:0] will both be 0
during the address phase indicating a linear burst or-
der. Note that during a burst read operation, all byte
lanes will always be active. The Am79C973/
Am79C975 controller will internally discard unneeded
bytes.
The Am79C973/Am79C975 controller will always per-
form only a single burst read transaction per bus mas-
tership period, where
transaction
is defined as one
address phase and one or multiple data phases. The
Am79C973/Am79C975 controller supports zero wait
state read cycles. It asserts IRDY immediately after the
address phase and at the same time starts sampling
DEVSEL. FRAME is deasserted when the next to last
data phase is completed.
Figure 13 shows a typical burst read access. The
Am79C973/Am79C975 controller arbitrates for the bus,
is granted access, reads three 32-bit words (DWord)
from the system memory, and then releases the bus. In
the example, the memory system extends the data
phase of each access by one wait state. The example
assumes that EXTREQ (BCR18, bit 8) is cleared to 0,
therefore, REQ is deasserted in the same cycle as
FRAME is asserted.
FRAME
CLK
AD
IRDY
C/
BE
REQ
GNT
1
2
3
4
5
CMD
ADDR
21510D-16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C976 | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
| AM79C973/AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973AVC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973BKC | 制造商:Advanced Micro Devices 功能描述:79C973BKC |