參數(shù)資料
型號(hào)： AMC1210IRHAT
英文描述： Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
中文描述： 四數(shù)字濾波器2階Δ-Σ調(diào)制器
文件頁(yè)數(shù)： 13/47頁(yè)
文件大?。?/td> 805K
代理商： AMC1210IRHAT
www.ti.com
Clock Setup
The clock pin CLK controls the timing of several functions.
Table 4
shows the units and features that use the
CLK signal for timing.
SPI Mode
The SPI interface runs fully asynchronously to the rest of the system. The four signals of the SPI interface are
WR, RD, AD0 and CS. The maximum speed of the SPI interface is 40MHz. When the select signal CS is high,
the entire SPI interface is in reset state, except the Address and the Data Register. The SPI clock WR and the
serial data input RD are disabled when CS is high. The incoming data is strobed by the SPI interface on the
falling edge of the WR. Outgoing data is put on the output AD0 on the rising edge of the WR (see
SPI Interface
Modes
). For a transmission of one 16-bit data word, 24 bits are required. The first incoming bit to the AMC1210
determines if the entire transmission is a read or a write operation. A high bit indicates a read operation, and a
low bit indicates a write operation. There are seven address bits. The 16 data bits are transmitted or received
after the address bits, according to the sequence shown in
Table 5
.
SPI Option 1
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
Table 4. CLK Pin Functions
MODULE/UNIT
Interface/Signal Generator
FEATURE
CLOCK FUNCTION
Signal generator
Manchester Decoder in control unit
CLKx signal in control unit
Determines output data rate
Allows decoding of Manchester data
Provides timing for CLKx pin when bit CD in the control
parameter = '1'
Divides CLKx speed
Allows AMC1210 to monitor input clock CLKx
TMU counts number of CLK cycles when TM = 0
Filter/Input Control
Clock dividers for CLKx in control unit
Modulator failure detection
Time measurement
Filter/Time Measurement
If none of the features in this table are needed, the CLK pin should be connected to GND to avoid any increased
current consumption.
Table 5. SPI Write 24-Bit Word Format
MSB
A15
LSB
A0
A24
A23
A22
A21
A20
A19
A18
A17
A16
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
R/W
Address
Data
In SPI option 1, one 16-bit transfer is accomplished in the following manner:
1. On the first falling edge of WR, the read/write bit is strobed.
2. On the second falling edge of WR, the MSB of the address (bit 6) is strobed.
3. On the eighth falling edge of WR, the LSB of the address (bit 0) is strobed and the corresponding data of the
register map is read.
4. On the ninth rising edge (MSB), the data read from the register map is latched into a shift register and
shifted one position each rising edge of the WR. At speeds below 25MHz, it is recommended to perform a
read on the next falling edge (Option 1). This data is always sent out, even when a write operation is
performed.
5. On the 24th falling edge of WR (LSB), the last data bit is shifted in from RD and a write pulse is generated
to write the data into the register map, if a write operation was performed.
Figure 2
and
Figure 3
provide detailed timing information for the SPI modes.
13
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