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| 型號： | AMC1210IRHAT |
| 英文描述： | Quad Digital Filter for 2nd-Order Delta-Sigma Modulator |
| 中文描述： | 四數(shù)字濾波器2階Δ-Σ調(diào)制器 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大?。?/td> | 805K |
| 代理商： | AMC1210IRHAT |
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Mode 1 (TM = 1)
SH1
or
SH2
TIMER
TIME
REGISTER
CLKx
2
3
1
61
63
64
62
65
66
67
125
127
128
126
1
2
3
Previous Value
128
61
63
64
62
65
66
67
68
70
71
69
MODE 1 (TM = 1)
Mode 2 (TM = 0)
ACK
TIMER
TIME
REGISTER
MODE 2 (TM = 0)
CLKx
2
3
1
1
3
...
2
...
...
...
125
127
128
129
126
1
Previous Value
128
2
63
64
3
65
66
67
67
68
70
71
69
SH1
or
SH2
DATA
REGISTER
Data Valid
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
In Mode 1, the time measure unit updates the
Time Register
with the elapsed amount of incoming modulator
clock cycles between two rising edges of the selected sample-and-hold signal (selected by the SHS bit of the
Control Parameter Register
). This mode can be used to measure the speed of the modulator clock or determine
the number of input bits that have been clocked into the filter module. Each time a positive edge of the selected
sample-and-hold is detected, the
Time Register
will be updated with the time counter value, and the time
counter will be reset.
Figure 18
shows an example of a typical functional timer sequences in Mode 1.
Figure 18. Typical Functional Timer Sequence, Mode 1 (TM = 1)
In Mode 2, the time measure unit updates the
Time Register
with the elapsed amount of system clock cycles
from the last available data to the next rising edge of the selected sample-and-hold signal. Each time data is
available, that is, when the sinc filter or the integrator has new data, the timer will reset. The timer continuously
counts when a rising edge of the selected sample-and-hold signal occurs. At this point, the
Time Register
is
updated with the time counter value, and the time counter will be reset.
Figure 19
shows an example of a typical
functional timer sequence in Mode 2.
Since the
Time Register
is a 16-bit register, the maximum time measured is 65,536 clock cycles. The bit TOx in
the
Status Register
is set to high when the time counter receives an overflow (that is, when the counter changes
from 0xFFFF to 0x0000). This status bit is reset when the
Status Register
is read.
Figure 19. Typical Functional Timer Sequence, Mode 2 (TM = 0)
23
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