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參數(shù)資料
| 型號(hào)： | AMC1210IRHAT |
| 英文描述： | Quad Digital Filter for 2nd-Order Delta-Sigma Modulator |
| 中文描述： | 四數(shù)字濾波器2階Δ-Σ調(diào)制器 |
| 文件頁數(shù)： | 25/47頁 |
| 文件大?。?/td> | 805K |
| 代理商： | AMC1210IRHAT |
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Driving a Signal with the Signal Generator
Interrupt Unit
Figure 21
shows the structure of the interrupt unit.
HLT1
COMP1
COMPH1
COMPL1
LLT1
MIE
MIE
IEH1
IEH1
IEL1
IEL1
MIE
MIE
S
R
S
R
Q
QIFH1
IFL1
> 1
IP
INT Pin
= 1
Signal when
Interrupt Register is read
From the
other filter units
From the
watchdog timers
Acknowledge
The acknowledge pin ACK indicates that new data is available from one of the filter modules. When the
acknowledge pin goes high, new data is available in one or more of the Data Registers. By reading the
Interrupt
Register
, the filter module with new data can be determined. When one Data Register is read, the appropriate
acknowledge flag in the
Interrupt Register
will be reset; when all flags are reset, the acknowledge pin is reset to
low. The acknowledge pin can be inverted if the acknowledge polarity control bit (AP) in the
Control Register
is
set high. The acknowledge flags cannot be set if both the sinc filter and the integrator are disabled. Each
acknowledge flag can be disabled if the Acknowledge Enable control bit (AE) in the appropriate Sinc Filter
Parameter Register is set to low. The acknowledge flag is not set when the oversampling rates of the sinc filter
and the integrator are both set to '1'.
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
CONTROL AND INTERRUPT MODULE (continued)
The resolver can be driven directly from the AMC1210. If the bit HBE is set to high, the pins PWM1 and PWM2
are capable of driving 100mA directly into the resolver coils. If bit HBE = 0, the drive capability is lowered.
The pattern generator is enabled by the bit SGE in the
Clock Divider Register
.
Figure 21. AMC1210 Interrupt Unit
Each comparator output is one interrupt source (COMPHx or COMPLx) creating eight total comparator outputs
in the AMC1210. Each of these eight interrupt sources is stored in a flag register (IFHx or IFLx), if the master
interrupt enable (MIE) and the appropriate interrupt enable (IEHx or IELx) are set to high. This flag register will
be set to high if an interrupt is issued. This flag will be reset if the
Interrupt Register
is read and the interrupt
source is no longer active. If an interrupt source is still active when the
Interrupt Register
is read, the appropriate
flag will remain set.
If the modulator clock is failing (when the modulator clock is slower than 1/64th of the system clock CLK), a
watchdog timer will set a flag MFx, if the appropriate modulator flag interrupt enable bit (MFIEx) and the master
interrupt enable (MIE) is set. If the modulator clock is still failing when the
Interrupt Register
is read, the
appropriate flag remains set. The flag clears if the fail condition is no longer true, and the
Interrupt Register
is
read.
Any of the 12 interrupt bits will activate the interrupt pin INT, if enabled. The polarity of the INT pin can be
chosen with the Interrupt polarity control bit (IP) in the
Control Register
.
25
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