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| 型號： | AMC1210IRHAT |
| 英文描述： | Quad Digital Filter for 2nd-Order Delta-Sigma Modulator |
| 中文描述： | 四數(shù)字濾波器2階Δ-Σ調(diào)制器 |
| 文件頁數(shù)： | 8/47頁 |
| 文件大?。?/td> | 805K |
| 代理商： | AMC1210IRHAT |
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PARALLEL MODE 1
TIMING CHARACTERISTICS
(1)
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, BVDD = +2.7V, unless otherwise noted.
AD(7:0)
Internal address
ADDR
ADDR
ADDR+1
MSB
LSB
MSB
t
w1
t
w2
t
d1
t
d2
t
w3
t
su1
t
h1
t
su2
t
h2
Parallel mode 1, write access
t
w4
CS
WR
RD
ALE
ADDR
MSB
LSB
MSB
ADDR
ADDR+1
AD(7:0)
Internal address
Parallel mode 1, read access
t
d3
t
d4
t
w5
t
d5
t
d6
t
w6
t
d7
CS
WR
RD
ALE
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
PARAMETER
(2)
MIN
MAX
UNIT
t
w1
t
w2
t
d1
t
d2
t
w3
t
w4
t
su1
t
h1
t
su2
t
h2
t
d3
t
d4
t
w5
t
w6
t
d5
t
d6
t
d7
CS low width
40
ns
CS high width
5
ns
Delay time from CS low to WR low
3
ns
Delay time from WR high to CS high
5
ns
WR low width
10
ns
WR high width
10
ns
Setup time from ALE high to WR low
0
ns
Hold time from WR high to ALE low
2
ns
Setup time from address valid to WR high
6
ns
Hold time from WR high to address invalid
5
ns
Delay time from CS low to RD low
0
ns
Delay time from RD high to CS high
6
ns
RD low width
30
ns
RD high width
13
ns
Delay time from RD low to data valid
30
ns
Delay time from RD high to databus in tristate
0
10
ns
Delay time from WR high to RD low
10
ns
(1)
(2)
All input signals are specified with t
= t
= 5ns (10% to 90% of BVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
t
w2
is obsolete if CS stays low between the WR and RD pulses.
Figure 4. Parallel Mode 1 Timing
8
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