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參數(shù)資料
| 型號(hào)： | AMC1210IRHAT |
| 英文描述： | Quad Digital Filter for 2nd-Order Delta-Sigma Modulator |
| 中文描述： | 四數(shù)字濾波器2階Δ-Σ調(diào)制器 |
| 文件頁數(shù)： | 37/47頁 |
| 文件大小： | 805K |
| 代理商： | AMC1210IRHAT |
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Example 2: AMC1210 Configuration with 8kHz Carrier Frequency and 32MHz System Clock Frequency
Motor control loop frequency
f
CARRIER
8kHz
f
CLK
32MHz
(3)
(4)
f
CARRIER
f
CLK
N
CDiv
N
PAT
32MHz
N
CDiv
1000
(5)
CLK_Divider
f
CLK
f
CARRIER
N
PAT
32MHz
8kHz
1000
4
(6)
E
OSR
1
10
100
1000
16
14
12
10
8
6
4
2
0
Sinc
1
Sinc
2
Sinc
3
Sincfast
ADS1205
f
MODULATOR
f
CARRIER
SOSR
ISOR
N
INT
(7)
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
The carrier frequency is generated using the signal generator, which uses the CLK signal for timing. In order to
achieve optimal resolution on the carrier signal, it is recommended to use the largest number of bits possible, up
to 1024, for a single cycle of the carrier signal. In this example, the length of the signal generator (PC9–PC0 in
the
Control Register
) was chosen to be 1000. This length means the carrier frequency will be:
Now the Clk_divider value for the signal generator (SD3–SD0 in the
Clock Divider Register
) can be calculated:
Therefore, the user can generate a carrier frequency of 8kHz using a CLK speed of 32MHz, and programming
bits PC9–PC0 to 999 (1000 – 1) and bits SD3–SD0 to 3 (4 – 1).
The next matter of importance is to determine the optimal speed versus resolution tradeoff on the modulator.
Figure 23
shows the tradeoff in performance for speed on the ADS1205 modulator. A higher OSR can provide
increased ENOB (effective number of bits); however, it requires more data from the converter, resulting in an
increased filter delay.
Figure 23. Effective Number of Bits vs Oversampling Ratio (ADS1205)
For maximum resolution, it is best to run the modulator as fast as possible. The speed of the modulator
determines what oversampling ratio is needed on the sinc filter and the integrator. In order to synchronize to the
motor control loop, the modulator must be decimated down by an integer divisor of the modulator frequency.
This relationship is given in
Equation 7
.
Where
N
INT
is the number of carrier signal cycles that will be integrated over. This value is usually set to 1.
37
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