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參數(shù)資料
| 型號： | AN10E40 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Field Programmable Analog Array |
| 中文描述： | 現(xiàn)場可編程模擬陣列 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大小： | 293K |
| 代理商： | AN10E40 |
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Field Programmable
Analog Array
The AN10E40 brings to analog what FPGAs brought to digital; extremely rapid production and prototype circuit
realization with field re-programmability. The AN10E40 consists of a 4 x 5 matrix of fully configurable switched
capacitor cells, enmeshed in a fabric of programmable interconnect resources. These programmable features are
directed by an on-chip SRAM configuration memory. The SRAM configuration memory is initialized on power up
via an on off chip serial PROM or through the AN10E40’s standard microprocessor peripheral interface.
A configuration memory image is easily constructed using the companion AnadigmDesigner software which
includes an extensive library of adjustable, proven, pre-built functions. The configurable analog blocks are often
consumed one at a time, though some of the more complex library functions may consume two or more blocks.
Specialized IO cells surround the core to bring your analog signals in and out of the array.
The AN10E40 coupled with the intuitive AnadigmDesigner software gives both digital and analog designers a
competitive advantage in designing analog circuits that can’t really be compared to any other design system in
existence. Quickly constructed, accurate, drift free, temperature compensated and
programmable
analog circuits
are now yours. Imagine the power of programmable with the versatility of analog.
Benefits
Extremely Rapid Analog Design – Minutes not weeks to re-spin a new design idea
In Circuit Programmable – Behavior can be changed as fast as 125 microseconds
Re-Configurable Using Conventional Logic, Serial PROMs or Microcontrollers
Extremely Stable over Voltage and Temperature
No Component Aging
Reliable and Repeatable Performance
Flexible Internal Clock and Routing Resources
No More Trimming Components
No More Tuning Components
AN10E40
Preliminary Information
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Config. Logic
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Configuration Data Shift Register
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