參數資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數： 122/173頁
文件大?。?/td> 897K
代理商： ARM610
Memory Management Unit
ARM610 Data Sheet
9-18
9.17 Interaction of the MMU, IDC and Write Buffer
The MMU, IDC and WB may be enabled/disabled independently. However there are
only five valid combinations. There are no hardware interlocks on these restrictions, so
invalid combinations will cause undefined results.
The following procedures must be observed.
To enable the MMU
1
Program the Translation Table Base and Domain Access Control Registers
2
Program Level 1 and Level 2 page tables as required
3
Enable the MMU by setting bit 0 in the Control Register
Care must be taken if the translated address differs from the untranslated address, as
the two instructions following the enabling of the MMU will have been fetched using
“flat translation” and enabling the MMU may be considered as a branch with delayed
execution. A similar situation occurs when the MMU is disabled. Consider the following
code sequence:
Note
MOV R1, #0x1
MCR 15,0,R1,0,0
Fetch Flat
Fetch Flat
Fetch Translated
; Enable MMU
To disable the MMU
1
Disable the WB by clearing bit 3 in the Control Register.
2
Disable the IDC by clearing bit 2 in the Control Register.
3
Disable the MMU by clearing bit 0 in the Control Register.
MMU
IDC
WB
off
off
off
on
off
off
on
on
off
on
off
on
on
on
on
Figure 9-11: Valid MMU, IDC and write buffer combinations
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