- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378406 > ARM610 (Zarlink Semiconductor Inc.) General purpose 32-bit microprocessor PDF資料下載
參數(shù)資料
| 型號： | ARM610 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁數(shù)： | 143/173頁 |
| 文件大?。?/td> | 897K |
| 代理商： | ARM610 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁當(dāng)前第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁
Boundary-Scan Test Interface
ARM610 Data Sheet
11-9
In TEST mode (ie. when either EXTEST or INTEST is the currently selected
instruction), values can be applied to the core logic or output pins independently of the
actual values on the input pins and core logic outputs respectively. On the ARM610,
all of the boundary-scan cells include an update register and thus all of the pins can
be controlled in the above manner. Additional boundary-scan cells are interposed in
the scan chain in order to control the enabling of tristateable buses.
The correspondence between boundary-scan cells and system pins, system direction
controls and system output enables is as shown in
·
Table 11-3: Boundary-scan
signals and pinson page 11-12. The cells are listed in the order in which they are
connected in the boundary-scan register, starting with the cell closest to
TDI
. All
boundary-scan register cells at input pins can apply tests to the on-chip core logic.
The EXTEST guard values specified in
·
Table 11-3: Boundary-scan signals and pins
on page 11-12 should be clocked into the boundary-scan register (using the SAMPLE/
PRELOAD instruction) before the EXTEST instruction is selected, to ensure that
known data is applied to the core logic during the test. The INTEST guard values
shown in the table below should be clocked into the boundary-scan register (using the
SAMPLE/PRELOAD instruction) before the INTEST instruction is selected to ensure
that all outputs are disabled. These guard values should also be used when new
EXTEST or INTEST vectors are clocked into the boundary-scan register.
The values stored in the BS register after power-up are not defined. Similarly, the
values previously clocked into the BS register are not guaranteed to be maintained
across a Boundary-Scan reset (from forcing nTRST LOW or entering the Test Logic
Reset state).
11.7.4 Output Enable Boundary-Scan cells
The boundary-scan register cells Nendout, Nabe, Ntbe, and Nmse control the output
drivers of tristate outputs as shown in the table below. In the case of OUTEN0 enable
cells (Nendout, Ntbe), loading a 1 into the cell will place the associated drivers into the
tristate state, while in the case of type INEN1 enable cells (Nabe, Nmse), loading a 0
into the cell will tristate the associated drivers.
To put all ARM610 tristate outputs into their high impedance state, a logic 1 should be
clocked into the output enable boundary-scan cells Nendout and Ntbe, and a logic 0
should be clocked into Nabe and Nmse. Alternatively, the HIGHZ instruction can be
used.
If the on-chip core logic causes the drivers controlled by Nendout, for example, to be
tristate, (ie. by driving the signal Nendout HIGH), then a 1 will be observed on this cell
if the SAMPLE/PRELOAD or INTEST instructions are active.
11.7.5 Single-step operation
ARM610 is a static design and there is no minimum clock speed. It can therefore be
single-stepped while the INTEST instruction is selected. This can be achieved by
serialising a parallel stimulus and clocking the resulting serial vectors into the
boundary-scan register. When the boundary-scan register is updated, new test stimuli
are applied to the core logic inputs; the effect of these stimuli can then be observed on
the core logic outputs by capturing them in the boundary-scan register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ARM7TDMI | 32-Bit Advanced RISC Machines(ARM) Microprocessor Core(32位ARM微處理器內(nèi)核芯片) |
| ART10012T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART10015T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART2812T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART28XXT | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM7-009 | 制造商:Gravitech 功能描述:ARM7 LPC2378 W/2.8" TCH SCRN LCD BLU |
| ARM720T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip |
| ARM7DIMM-LPC2478 | 功能描述:模塊化系統(tǒng) - SOM LPC2478 ARM7 DIMM Module, Rev 2.2 RoHS:否 制造商:Digi International 外觀尺寸:ConnectCore 9P 處理器類型:ARM926EJ-S 頻率:150 MHz 存儲容量:8 MB, 16 MB 存儲類型:NOR Flash, SDRAM 接口類型:I2C, SPI, UART 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 尺寸:1.97 in x 1.97 in x 6.1 in |
| ARM7TDI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM7TDMI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:general purpose 32-bit microprocessors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。