參數(shù)資料
型號： ARM610
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 23/173頁
文件大?。?/td> 897K
代理商： ARM610
Programmer’s Model
ARM610 Data Sheet
3-7
When an IRQ is detected, ARM610 performs the following:
1
Saves the address of the next instruction to be executed plus 4 in R14_irq;
saves CPSR in SPSR_irq
2
Forces M[4:0]=10010 (IRQ mode) and sets the I bit in the CPSR
3
Forces the PC to fetch the next instruction from address 0x18
To return normally from IRQ, use SUBS PC,R14_irq,#4 which will restore both the PC
and the CPSR and resume execution of the interrupted code.
3.5.3 Abort
An
the external
be completed. For instance, in a virtual memory system the data corresponding to the
current address may have been moved out of memory onto a disc, and considerable
processor activity may be required to recover the data before the access can be
performed successfully. ARM610 checks for ABORT during memory access cycles.
When successfully
aborted ARM610 will respond in one of two ways:
ABORT can be signalled by either the internal Memory Management Unit or from
ABORT
input. ABORT indicates that the current memory access cannot
1
If the
prefetched instruction is marked as invalid but the
occur immediately. If the instruction is not executed, for example as a result of
a branch being taken while it is in the pipeline, no
will take place if the instruction reaches the head of the pipeline and is about
to be executed.
abort occurred during an instruction prefetch (a
Prefetch
abort exception does not
Abort
), the
abort will occur. An
abort
2
If the
on the instruction type.
abort occurred during a data access (a
Dat
a
Abort
), the action depends
a)
Single data transfer instructions (LDR, STR) are
instruction had not executed if the processor is configured for Early
When configured for Late
Abort, these instructions are able to write back
modified base registers and the Abort handler must be aware of this.
aborted as though the
Abort.
b)
The swap instruction (SWP) is
though externally the read access may take place.
aborted as though it had not executed,
c)
Block data transfer instructions (LDM, STM) complete, and if write-back is
set, the base is updated. If the instruction would normally have overwritten
the base with data (i.e. LDM with the base in the transfer list), this
overwriting is prevented. All register overwriting is prevented after the
Abort is indicated, which means in particular that R15 (which is always
last to be transferred) is preserved in an aborted LDM instruction.
Note that on Data Aborts the ARM610 fault address and fault status registers are
updated.
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