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參數(shù)資料
| 型號： | ARM610 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁數(shù)： | 60/173頁 |
| 文件大?。?/td> | 897K |
| 代理商： | ARM610 |
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Instruction Set - LDR, STR
ARM610 Data Sheet
4-32
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4.8.2 Halfword load and stores
Setting S=0 and H=1 may be used to transfer unsigned halfwords between an
ARM610 register and memory.
The action of LDRH and STRH instructions is influenced by the BIGEND control
signal. The two possible configurations are described in the section below.
4.8.3 Signed byte and halfword loads
The S bit controls the loading of sign-extended data. When S=1 the H bit selects
between Bytes (H=0) and halfwords (H=1). The L bit should not be set low (Store)
when Signed (S=1) operations have been selected.
The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination
register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign
bit.
The LDRSH instruction loads the selected halfword into bits 15 to 0 of the destination
register and bits 31 to 16 of the destination register are set to the value of bit 15, the
sign bit.
The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control
signal. The two possible configurations are described in the following section.
4.8.4 Endianness and byte/halfword selection
Little-endian configuration
A signed byte load (LDRSB) expects data on data bus inputs 7 through to 0 if the
supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a
word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit
of the destination register, and the remaining bits of the register are filled with the sign
bit, bit 7 of the byte. Please see
·
Figure 3-2: Little endian addresses of bytes within
wordson page 3-3
A halfword load (LDRSH or LDRH) expects data on data bus inputs 15 through to 0 if
the supplied address is on a word boundary and on data bus inputs 31 through to 16
if it is a halfword boundary, (A[1]=1).The supplied address should always be on a
halfword boundary. If bit 0 of the supplied address is HIGH, the ARM610 will load an
unpredictable value. The selected halfword is placed in the bottom 16 bits of the
destination register. For unsigned halfwords (LDRH), the top 16 bits of the register are
filled with zeros and for signed halfwords (LDRSH) the top 16 bits are filled with the
sign bit, bit 15 of the halfword.
A halfword store (STRH) repeats the bottom 16 bits of the source register twice across
the data bus outputs 31 through to 0. The external memory system should activate the
appropriate halfword subsystem to store the data. Note that the address must be
halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable
behaviour.
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