參數(shù)資料
型號(hào)： AT80C51RD2-SLSUM
廠商： Atmel
文件頁(yè)數(shù)： 3/81頁(yè)
文件大?。?/td> 0K
描述： IC 8051 MCU 5V SPI 20MHZ 44-PLCC
標(biāo)準(zhǔn)包裝： 972
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-PLCC
包裝： 管件
11
4113D–8051–01/09
AT80C51RD2
Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)
Not bit addressable
5
PCAX2
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4SIX2
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3T2X2
Timer 2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1T0X2
Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
0X2
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual
peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Config Byte (HCB).
Bit
Number
Bit
Mnemonic
Description
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