參數(shù)資料
型號(hào): AT80C51RD2-SLSUM
廠商: Atmel
文件頁數(shù): 40/81頁
文件大小: 0K
描述: IC 8051 MCU 5V SPI 20MHZ 44-PLCC
標(biāo)準(zhǔn)包裝: 972
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-PLCC
包裝: 管件
45
4113D–8051–01/09
AT80C51RD2
12. Interrupt System
The AT80C51RD2 have a total of 8 interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (timers 0, 1 and 2), the serial port interrupt, Keyboard interrupt and the
PCA global interrupt. These interrupts are shown in Figure 12-1.
Figure 12-1. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (Table 12-5 and Table 12-3). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source also can be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (Table 12-6) and in the Interrupt Priority
High register (Table 12-4 and Table 12-5) shows the bit values and priority levels associated
with each combination.
12.1
Registers
The PCA interrupt vector is located at address 0033H, the Keyboard interrupt vector is located
at address 004BH. All other vectors addresses are the same as standard C52 devices.
IE1
0
3
High Priority
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
Low Priority
Interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
0
3
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