參數(shù)資料
型號(hào)： AT80C51RD2-SLSUM
廠商： Atmel
文件頁數(shù)： 41/81頁
文件大?。?/td> 0K
描述： IC 8051 MCU 5V SPI 20MHZ 44-PLCC
標(biāo)準(zhǔn)包裝： 972
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-PLCC
包裝： 管件
46
4113D–8051–01/09
AT80C51RD2
Table 12-1.
Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 12-2.
IEO Register
IE0 - Interrupt Enable Register (A8h)
IPH.x
IPL.x
Interrupt Level Priority
00
0 (Lowest)
011
102
1
3 (Highest)
76
543
210
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
7EA
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
6EC
PCA interrupt enable bit
Cleared to disable.
Set to enable.
5ET2
Timer 2 overflow interrupt enable bit
Cleared to disable Timer 2 overflow interrupt.
Set to enable Timer 2 overflow interrupt.
4ES
Serial port enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3ET1
Timer 1 overflow interrupt enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 overflow interrupt enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
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