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參數(shù)資料
| 型號： | AT80C51RD2-SLSUM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 52/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU 5V SPI 20MHZ 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 972 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-PLCC |
| 包裝： | 管件 |
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56
4113D–8051–01/09
AT80C51RD2
14. Power Management
14.1
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed before
going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but not to the
interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack
Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain
their data during idle. The port pins hold the logical states they had at the time Idle was acti-
vated. ALE and PSEN hold at logic high level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced,
and following RETI the next instruction to be executed will be the one following the instruction
that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during nor-
mal operation or during idle. For example, an instruction that activates idle can also set one or
both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine
the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-
tor periods) to complete the reset.
14.2
Power-down Mode
To save maximum power, a power-down mode can be invoked by software (refer to Table 11-
12, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down
mode is the last instruction executed. The internal RAM and SFRs retain their value until the
power-down mode is terminated. V
CC can be lowered to save further power. Either a hardware
reset or an external interrupt can cause an exit from power-down. To properly terminate power-
down, the reset or external interrupt should not be executed before V
CC is restored to its normal
operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from power-down.
Thus, the interrupt must be enabled and configured as level - or edge - sensitive interrupt input.
When Keyboard Interrupt occurs after a power-down mode, 1024 clocks are necessary to exit to
power-down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed
in Figure 14-1. When both interrupts are enabled, the oscillator restarts as soon as one of the
two inputs is held low and power-down exit will be completed when the first input is released. In
this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced,
the next instruction to be executed after RETI will be the one following the instruction that put
AT80C51RD2 into power-down mode.
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