參數(shù)資料
型號: AT91M55800A-33CJ SL383
廠商: Atmel
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC ARM MCU 16BIT 176BGA
標(biāo)準(zhǔn)包裝: 1,000
系列: AT91
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 58
程序存儲器類型: ROMless
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b; D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 176-LFBGA
包裝: 帶卷 (TR)
配用: AT91EB55-ND - KIT EVAL FOR ARM AT91M55800A
其它名稱: AT91M55800A33CJSL
19
1745FS–ATARM–18-Apr-06
AT91M55800A Summary
Most importantly, the PDC removes the processor interrupt handling overhead and signifi-
cantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K
contiguous bytes. As a result, the performance of the microcontroller is increased and the
power consumption reduced.
8.1
System Peripherals
8.1.1
APMC: Advanced Power Management Controller
The AT91M55800A Advanced Power Management Controller allows optimization of power
consumption. The APMC enables/disables the clock inputs of most of the peripherals and the
ARM core. Moreover, the main oscillator, the PLL and the analog peripherals can be put in
standby mode allowing minimum power consumption to be obtained. The APMC provides the
following operating modes:
Normal mode: clock generator provides clock to the entire chip except the RTC.
Wait mode: ARM core clock deactivated
Slow Clock mode: clock generator deactivated, master clock 32 kHz
Standby mode: RTC active, all other clocks disabled
Power-down mode: RTC active, supply on the rest of the circuit deactivated
8.1.2
RTC: Real Time Clock
The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for very low
power consumption. It combines a complete time-of-day clock with alarm and a two-hundred
year Gregorian calendar, complemented by a programmable periodic interrupt.
The time and calendar values are coded in Binary-Coded Decimal (BCD) format. The time for-
mat can be 24-hour mode or 12-hour mode with an AM/PM indicator.
Updating time and calendar fields and configuring the alarm fields is performed by a parallel
capture on the 32-bit data bus. An entry control is performed to avoid loading registers with
incompatible BCD format data or with an incompatible date according to the current month/
year/century.
8.1.3
AIC: Advanced Interrupt Controller
The AIC has an 8-level priority, individually maskable, vectored interrupt controller, and drives
the NIRQ and NFIQ pins of the ARM7TDMI from:
The external fast interrupt line (FIQ)
The six external interrupt request lines (IRQ0 - IRQ5)
The interrupt signals from the on-chip peripherals
The AIC is largely programmable offering maximum flexibility, and its vectoring features
reduce the real-time overhead in handling interrupts.
The AIC also features a spurious vector, which reduces spurious interrupt handling to a mini-
mum, and a protect mode that facilitates the debug capabilities.
8.1.4
PIO: Parallel I/O Controller
The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as general-purpose
I/O pins. The other I/O lines are multiplexed with an external signal of a peripheral to optimize
the use of available package pins. The PIO lines are controlled by two separate and identical
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