參數(shù)資料
型號: AT91M55800A-33CJ SL383
廠商: Atmel
文件頁數(shù): 14/28頁
文件大?。?/td> 0K
描述: IC ARM MCU 16BIT 176BGA
標(biāo)準(zhǔn)包裝: 1,000
系列: AT91
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 58
程序存儲器類型: ROMless
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b; D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 176-LFBGA
包裝: 帶卷 (TR)
配用: AT91EB55-ND - KIT EVAL FOR ARM AT91M55800A
其它名稱: AT91M55800A33CJSL
21
1745FS–ATARM–18-Apr-06
AT91M55800A Summary
8.2
User Peripherals
8.2.1
USART: Universal Synchronous/
Asynchronous Receiver Transmitter
The AT91M55800A provides three identical, full-duplex, universal synchronous/asynchronous
receiver/transmitters.
Each USART has its own baud rate generator, and two dedicated Peripheral Data Controller
channels. The data format includes a start bit, up to 8 data bits, an optional programmable par-
ity bit and up to 2 stop bits.
The USART also features a Receiver Timeout register, facilitating variable-length frame sup-
port when it is working with the PDC, and a Time-guard register, used when interfacing with
slow remote equipment.
8.2.2
TC: Timer/Counter
The AT91M55800A features two Timer/Counter blocks that include three identical 16-bit
timer/counter channels. Each channel can be independently programmed to perform a wide
range of functions including frequency measurement, event counting, interval measurement,
pulse generation, delay timing and pulse-width modulation.
The Timer/Counters can be used in Capture or Waveform mode, and all three counter chan-
nels can be started simultaneously and chained together.
8.2.3
SPI: Serial Peripheral Interface
The SPI provides communication with external devices in master or slave mode. It has four
external chip selects that can be connected to up to 15 devices. The data length is program-
mable, from 8- to 16-bit.
8.2.4
ADC: Analog-to-digital Converter
The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Succes-
sive Approximation Register (SAR) approach.
Each ADC has 4 analog input pins, AD0 to AD3 and AD4 to AD7, digital trigger input
AD0TRIG and AD1TRIG pins, and provides an interrupt signal to the AIC. Both ADCs share
the analog power supply VDDA and GNDA pins, and the input reference voltage ADVREF pin.
Each channel can be enabled or disabled independently, and has its own data register. The
ADC can be configured to automatically enter Sleep Mode after a conversion sequence, and
can be triggered by the software, the Timer/Counter, or an external signal.
8.2.5
DAC: Digital-to-analog Converter
Two identical 1-channel 10-bit digital-to-analog converters (DAC).
Each DAC has an analog output pin, DA0 and DA1, and provides an interrupt signal to the AIC
DA0IRQ and DA1IRQ. Both DACs share the analog power supply VDDA and GNDA pins, and
the input reference DAVREF.
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