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參數(shù)資料
| 型號： | AT91M55800A-33CJ SL383 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM MCU 16BIT 176BGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | AT91 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 58 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b; D/A 2x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LFBGA |
| 包裝： | 帶卷 (TR) |
| 配用： | AT91EB55-ND - KIT EVAL FOR ARM AT91M55800A |
| 其它名稱： | AT91M55800A33CJSL |
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1745FS–ATARM–18-Apr-06
AT91M55800A Summary
7.3
Master Clock
Master Clock is generated in one of the following ways, depending on programming in the
APMC registers:
From the 32768 Hz low-power oscillator that clocks the RTC
The on-chip main oscillator, together with a PLL, generate a software-programmable main
clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to allow the user
to enter an external clock signal.
The Master Clock (MCK) is also provided as an output of the device on the MCKO pin, whose
state is controlled by the APMC module.
7.4
Reset
Reset restores the default states of the user interface registers (defined in the user interface of
each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address
zero. Aside from the program counter, the ARM7TDMI registers do not have defined reset
states.
7.4.1
NRST Pin
NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchro-
nized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768 Hz crystal),
and the signal presented on MCK must be active within the specification for a minimum of 10
clock cycles up to the rising edge of NRST, to ensure correct operation.
7.4.2
NTRST Pin
Test Access Port (TAP) reset functionality is provided through the NTRST signal.
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in
this reset is determined according to the initial logical state applied on the JTAGSEL pin after
the last valid NRST.
In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir-
cuitry, as shown in Figure 7-1 below. But in all cases, the NTRST like the NRST signal, must
be asserted after each power-up. (See the AT91M55800A electrical datasheet, Atmel lit°
1727, for the necessary minimum pulse assertion time.)
Figure 7-1.
Separate or Common Reset Management
Notes:
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
(1)
(2)
Reset
Controller
Reset
Controller
Reset
Controller
NTRST
NRST
NTRST
NRST
AT91M55800A
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| AT91M55800A-33CJ-T | 功能描述:IC MCU 32BIT ROMLESS 176LFBGA 制造商:microchip technology 系列:AT91 包裝:帶卷（TR） 零件狀態(tài):停產(chǎn) 核心處理器:ARM7? 核心尺寸:16/32-位 速度:33MHz 連接性:EBI/EMI，SPI，UART/USART 外設(shè):POR，WDT I/O 數(shù):58 程序存儲容量:- 程序存儲器類型:ROMless EEPROM 容量:- RAM 容量:8K x 8 電壓 - 電源（Vcc/Vdd）:2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b；D/A 2x10b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:176-LFBGA 供應(yīng)商器件封裝:176-LFBGA（11.2x11.2） 基本零件編號:AT91M55800 標(biāo)準(zhǔn)包裝:1,000 |
| AT91M63200 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M63200_99 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M63200-12AI-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ARM Thumb Microcontrollers |
| AT91M63200-25AC | 功能描述:IC MCU 32BIT ROMLESS 176TQFP 制造商:microchip technology 系列:AT91SAM 包裝:托盤 零件狀態(tài):停產(chǎn) 核心處理器:ARM7? 核心尺寸:16/32-位 速度:25MHz 連接性:EBI/EMI，SPI，UART/USART 外設(shè):POR，WDT I/O 數(shù):58 程序存儲容量:- 程序存儲器類型:ROMless EEPROM 容量:- RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器類型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:176-LQFP 供應(yīng)商器件封裝:176-TQFP（24x24） 基本零件編號:AT91M63200 標(biāo)準(zhǔn)包裝:40 |
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