參數(shù)資料
型號: ATTINY13V-10SSUR
廠商: Atmel
文件頁數(shù): 19/176頁
文件大小: 0K
描述: MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊: tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 4,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY13V-10SSUR-ND
ATTINY13V-10SSURTR
2010-2011 Microchip Technology Inc.
Preliminary
DS41430C-page 115
PIC16(L)F720/721
15.3.2
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 15-1.
EQUATION 15-1:
PWM PERIOD
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
TMR2 is cleared
The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPR1L into
CCPR1H.
15.3.3
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to multiple registers: CCPR1L register and DC1 and B1
bits of the CCP1CON register. The CCPR1L contains
the eight MSbs and the DC1 and B1 bits of the
CCP1CON register contain the two LSbs. CCPR1L and
DC1 and B1 bits of the CCP1CON register can be
written to at any time. The duty cycle value is not latched
into CCPR1H until after the period completes (i.e., a
match between PR2 and TMR2 registers occurs). While
using the PWM, the CCPR1H register is read-only.
Equation 15-2 is used to calculate the PWM pulse
width.
Equation 15-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 15-2:
PULSE WIDTH
EQUATION 15-3:
DUTY CYCLE RATIO
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (refer to
Note:
The
Timer2
postscaler
(refer
to
used in the determination of the PWM
frequency.
PWM Period
PR2
1
+
4TOSC
=
(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
Pulse Width
CCPR1L:CCP1CON<5:4>
=
TOSC
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC
Duty Cycle Ratio
CCPR1L:CCP1CON<5:4>
4PR2
1
+
-----------------------------------------------------------------------
=
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