參數(shù)資料
型號(hào): ATTINY13V-10SSUR
廠商: Atmel
文件頁數(shù): 59/176頁
文件大?。?/td> 0K
描述: MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊: tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 4,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲(chǔ)器容量: 1KB(512 x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY13V-10SSUR-ND
ATTINY13V-10SSURTR
2010-2011 Microchip Technology Inc.
Preliminary
DS41430C-page 151
PIC16(L)F720/721
17.2.4
ADDRESSING
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
line (SCL).
17.2.4.1
7-bit Addressing
In 7-bit Addressing mode (Figure 17-10), the value of
register SSPSR<7:1> is compared to the value of reg-
ister SSPADD<7:1>. The address is compared on the
falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
The SSPSR register value is loaded into the
SSPBUF register.
The BF bit is set.
An ACK pulse is generated.
SSP Interrupt Flag bit, SSPIF of the PIR1 register,
is set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
17.2.4.2
10-bit Addressing
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 17-11). The five Most
Significant bits (MSbs) of the first address byte specify
if it is a 10-bit address. The R/W bit of the SSPSTAT
register must specify a write so the slave device will
receive the second address byte. For a 10-bit address,
the first byte would equal ‘1111 0 A9 A8 0’, where
A9 and A8 are the two MSbs of the address.
The sequence of events for 10-bit address is as follows
for reception:
1.
Load SSPADD register with high byte of address.
2.
Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
3.
Read the SSPBUF register (clears bit BF).
4.
Clear the SSPIF flag bit.
5.
Update the SSPADD register with second (low)
byte of address (clears UA bit and releases the
SCL line).
6.
Receive low byte of address (bits SSPIF, BF and
UA are set).
7.
Update the SSPADD register with the high byte
of address. If match releases SCL line, this will
clear bit UA.
8.
Read the SSPBUF register (clears bit BF).
9.
Clear flag bit SSPIF.
If data is requested by the master, once the slave has
been addressed:
1.
Receive repeated Start condition.
2.
Receive repeat of high byte address with R/W = 1,
indicating a read.
3.
BF bit is set and the CKP bit is cleared, stopping
SCL and indicating a read request.
4.
SSPBUF is written, setting BF, with the data to
send to the master device.
5.
CKP is set in software, releasing the SCL line.
17.2.4.3
Address Masking
The Address Masking register (SSPMSK) is only
accessible while the SSPM bits of the SSPCON
register are set to ‘1001’. In this register, the user can
select which bits of a received address the hardware
will compare when determining an address match. Any
bit that is set to a zero in the SSPMSK register, the
corresponding bit in the received address byte and
SSPADD register are ignored when determining an
address match. By default, the register is set to all
ones, requiring a complete match of a 7-bit address or
the lower eight bits of a 10-bit address.
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