參數(shù)資料
型號(hào)： BXM80526B600128
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495
封裝： BGA2-495
文件頁(yè)數(shù)： 19/74頁(yè)
文件大?。?/td> 870K
代理商： BXM80526B600128
Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
19
Table 15. GTL+ Signal Groups AC Specifications
1
RTT =
56 internally terminated to V
CCT; VREF =
2/
3VCCT; load = 0 pF;
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T7
GTL+ Output Valid Delay
0.2
2.7
ns
T8
GTL+ Input Setup Time
1.2
ns
Notes 2, 3
T9
GTL+ Input Hold Time
0.80
ns
Note 4
T10
RESET# Pulse Width
1.0
ms
Note 5
NOTES:
1.
All AC timings for GTL+ signals are referenced to the BCLK rising edge at 1.25V. All GTL+ signals are referenced at
VREF.
2.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
3.
Specification is for a minimum 0.40V swing.
4.
Specification is for a maximum 1.0V swing.
5.
After VCC, VCCT, and BCLK become stable and PWRGOOD is asserted.
Table 16. CMOS and Open-drain Signal Groups AC Specifications
1, 2
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T14
1.5V Input Pulse Width, except PWRGOOD and
LINT[1:0]
2
BCLKs Figure 7
Active and
Inactive states
T14B
LINT[1:0] Input Pulse Width
6
BCLKs Figure 7
Note 3
T15
PWRGOOD Inactive Pulse Width
10
BCLKs Figure 10 Notes 4, 5
NOTES:
1.
All AC timings for CMOS and Open-drain signals are referenced to the BCLK rising edge at 1.25V. All CMOS and Open-
drain signals are referenced at 0.75V.
2.
Minimum output pulse width on CMOS outputs is 2 BCLKs.
3.
This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an edge
triggered interrupt with fixed delivery, otherwise specification T14 applies.
4.
When driven inactive, or after VCC, VCCT and BCLK become stable. PWRGOOD must remain below VIL25,max from Table 12
until all the voltage planes meet the voltage tolerance specifications in Table 9 and BCLK has met the BCLK AC
specifications in Table 13 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonically to 2.5V.
5.
If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD Inactive Pulse
Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain
below VIL25,max until all the voltage planes meet the voltage tolerance specifications.
Table 17. Reset Configuration AC Specifications
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T16
Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Setup Time
4BCLKs Figure 8.
Figure 9
Before
deassertion of
RESET#
T17
Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Hold Time
220
BCLKs Figure 8.
Figure 9
After clock that
deasserts
RESET#
T18
RESET#/PWRGOOD Setup Time
1
ms
deassertion of
RESET#
1
NOTE:
At least 1 ms must pass after PWRGOOD rises above VIH25,min from Table 12 and BCLK meets its AC timing
specification until RESET# may be deasserted.
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