參數(shù)資料
型號(hào)： BXM80526B600128
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 600 MHz, MICROPROCESSOR, PBGA495
封裝： BGA2-495
文件頁(yè)數(shù)： 30/74頁(yè)
文件大?。?/td> 870K
代理商： BXM80526B600128
Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
29
4.0
System Signal Simulations
Many scenarios have been simulated to generate a set of GTL+ processor system bus layout
guidelines, which are available in the Mobile Pentium III Processor GTL+ System Bus Layout
Guideline. Systems must be simulated using the IBIS model to determine if they are compliant
with this specification.
4.1
System Bus Clock (BCLK) and PICCLK AC Signal Quality
Specifications
Table 22 and Figure 15 show the signal quality for the system bus clock (BCLK) signal, and
Table 23 and Figure 15 show the signal quality for the APIC bus clock (PICCLK) signal at the
processor. BCLK and PICCLK are 2.5V clocks.
Table 22. BCLK Signal Quality Specifications
Symbol Parameter
Min
Max Unit
Figure
Notes
V1
VIL,BCLK
0.5
V
Note 1
V2
VIH,BCLK
2.0
V
Note 1
V3
VIN Absolute Voltage Range
-0.7
3.5
V
Undershoot/Overshoot,
Note 2
V4
BCLK Rising Edge Ringback
2.0
V
Absolute Value, Note 3
V5
BCLK Falling Edge Ringback
0.5
V
Absolute Value, Note 3
NOTES:
1.
The clock must rise/fall monotonically between
VIL,BCLK and VIH,BCLK.
2.
These specifications apply only when BCLK is running, see Table 12 for the DC specifications for when BCLK is stopped.
BCLK may not be above VIH,BCLK,max or below VIL,BCLK,min for more than 50% of the clock cycle.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the
BCLK signal can go to after passing the
VIH,BCLK (rising) or VIL,BCLK (falling) voltage limits.
Table 23. PICCLK Signal Quality Specifications
Symbol
Parameter
Min Max Unit Figure
Notes
V1
VIL25
0.7
V
V2
VIH25
2.0
V
V3
VIN Absolute Voltage Range
-0.7 3.5
V
Figure 15 Undershoot,Overshoot, Note 2
V4
PICCLK Rising Edge Ringback
2.0
V
Figure 15 Absolute Value, Note 3
V5
PICCLK Falling Edge Ringback
0.7
V
Figure 15 Absolute Value, Note 3
NOTES:
1.
The clock must rise/fall monotonically between VIL25 and VIH25.
2.
These specifications apply only when PICCLK is running, see Table 12 for the DC specifications for when PICCLK is
stopped. PICCLK may not be above VIH25,max or below VIL25,min for more than 50% of the clock cycle.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the
PICCLK signal can go to after passing the VIH25 (rising) or VIL25 (falling) voltage limits.
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