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C161U
Interrupt and Trap Functions
Data Sheet
115
2001-04-19
determines the minimum interrupt priority level that will be serviced. Any request on the
same or a lower level will not be acknowledged.
The current CPU priority level may be adjusted via software to control which interrupt
request sources will be acknowledged.
PEC transfers do not really interrupt the CPU, but rather “steal” a single cycle, so PEC
services do not influence the ILVL field in the PSW.
Hardware traps switch the CPU level to maximum priority (ie. 15) so no interrupt or PEC
requests will be acknowledged while an exception trap service routine is executed.
Note:
The TRAP instruction does not change the CPU level, so software invoked trap
service routines may be interrupted by higher requests.
Interrupt Enable bit IEN
globally enables or disables PEC operation and the
acceptance of interrupts by the CPU. When IEN is cleared, no interrupt requests are
accepted by the CPU. When IEN is set to '1', all interrupt sources, which have been
individually enabled by the interrupt enable bits in their associated control registers, are
globally enabled.
Note:
Traps are non-maskable and are therefore not affected by the IEN bit.
7.3
Operation of the PEC Channels
C161U's Peripheral Event Controller (PEC) provides 8 PEC service channels, which
move a single byte or word. This is the fastest possible interrupt response and in many
cases is sufficient to service the respective peripheral request (eg. serial channels, etc.).
Each channel is controlled by a dedicated PEC Channel Counter/Control register
(PECCx) and a pair of pointers for source (SRCPx) and destination (DSTPx) of the data
transfer.
The PECC registers control the action that is performed by the respective PEC channel.
Note:
For the PECCx register description, please also refer to page 88 of Sub-
Chapter "Extended PEC Channel Control".
Byte/Word Transfer bit BWT
controls, if a byte or a word is moved during a PEC service
cycle. This selection controls the transferred data size and the increment step for the
modified pointer.
Increment Control Field INC
controls, if one of the PEC pointers is incremented after
the PEC transfer. It is not possible to increment both pointers, however. If the pointers
are not modified (INC=’00’), the respective channel will always move data from the same
source to the same destination.
Note:
The reserved combination ‘11’ is changed to ‘10’ by hardware. However, it is not
recommended to use this combination.
The PEC Transfer Count Field COUNT controls the action of a respective PEC channel,
where the content of bit field COUNT at the time the request is activated selects the