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C161U
Power Reduction Modes
Data Sheet
376
2001-04-19
Note:
1)
: High if EINIT was executed before entering Idle or Power Down mode, Low otherwise.
2)
: For multiplexed buses with 8-bit data bus.
3)
: For demultiplexed buses.
4)
: The CS signal that corresponds to the last address remains active (low), all other
enabled CS signals remain inactive (high). By accessing an on-chip X-Periperal prior to
entering a power save mode all external CS signals can be deactivated.
19.4
Extended Power Management
Infineon Technologies C16x’s well known basic power reduction modes (Idle and Power
Down) are enhanced by a number of additional power management features. These
features can be combined or selectively used to reduce the controller’s power
consumption to the respective application’s possible minimum. According to the sense
of platform modularity, the extended power management functions are controlled by
different submodules and registers, as follows::
C161U’s power management functions can be supplemented by the Real Time Clock
(RTC) timer with optional periodic wakeup from Sleep or Idle mode. The periodic wakeup
combines the drastically reduced power consumption in power reduction modes (in
conjunction with the additional power management features) with a high level of system
availability. External signals and events can be scanned (at a lower rate) by periodically
activating the CPU and selected peripherals which then return to powersave mode after
a short time. This greatly reduces the system’s average power consumption. The RTC
is fully controlled by the C161U’s power reduction submodules.
The Extended Power Management Module controls the Sleep mode. The Sleep mode is
a new power management function which represents and is equal to a Power Down
mode but with exit/wakeup handling as in Idle mode. Wakeup out of Sleep state is
possible with all external interrupts (including alternate sources e.g. from ASC interface),
with NMI and with RTC interrupts. As in Idle mode also PEC requests are executed in
Sleep mode, resulting in an interruption and resumption of Sleep mode. The watchdog
timer is stopped in Sleep mode. The contents of internal RAM and of CBC’s registers are
preserved through the voltage supplied via the VDD pins.
As in Power Down mode, the Sleep mode may also be combined with a running real time
clock RTC. In Sleep mode the oscillators (RTC and selected oscillator optionally), the
Sub Module
Control Register
Extended Power Management /Sleep Mode Control
Flexible Clock Generation Management
Flexible Peripheral Management
SYSCON1
SYSCON2
SYSCON3