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C161U
External Bus Interface
Data Sheet
212
2001-04-19
windows than the standard ADDRSEL registers. As the register pairs control integrated
peripherals rather than externally connected ones, they are fixed by mask programming
rather than being user programmable.
X-Peripheral accesses provide the same choices as external accesses, so these
peripherals may be bytewide or wordwide, with or without a separate address bus.
Interrupt nodes and configuration pins (on PORT0) are provided for X-Peripherals to be
integrated.
10.8
Initialization of the C161U’s X-peripherals
The following registers must be set for initialization of the C161U X-peripherals:
XPERCON-Register (Addr. F024, default: 0000):
Bit 6:
'1': USB module active
Bit 7:
'1': EPEC active
'0': USB module switched-off
'0': EPEC switched-off
SYSCON-Register (Addr. FF12, default: 0xx0):
Bit 2:
'1': X-Peripherals enable
Bit 1:
'1': X-Per accesses visible at externalXBUS '0': X-Per accesses not visible
'0': X-Peripherals disable
SYSCON3-Register (Addr. F1D4, default: 0000):
Bit 15:
'1': All peripheral clocks disabled
'0': Individual disable control by
bits 14 thru 0
Bit 12:11: '00': USB transceiver in normal operation
’01’: Suspend mode, differential USB receiver switched off
’10’: Reserved, do not use this combination
’11’: USB transceiver switched off - full power down mode
Bit 8:
'1': Disable EPEC clock
Bit 7:
'1': Disable USB clock
Bit 3:
'1': Disable GPT12 clock
Bit 2:
'1': Disable SSC clock
Bit 1:
'1': Disable ASC clock
Bit 0:
'1': Disable RTC clock
'0': Enable EPEC clock
'0': Enable USB clock
'0': Enable GPT12 clock
'0': Enable SSC clock
'0': Enable ASC clock
'0': Enable RTC clock
XBCON1-Register (Addr.F114, default: 0000
H
):
This register is not used. Must be set to ’0000
H
’).
XBCON2-Register (Addr.F116, default: 0000
H
):
Definition of the USB bus protocol.
Must be set to ’048x
H
’. Recommended using 0 waitstates: ’048F
H
’.
XBCON3-Register (Addr.F118, default: 0000
H
):
Definition of the EPEC bus protocol.
Must be set to ’048x
H
’. Recommended using 0 waitstates: ’048F
H
’.