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CPU Multiply Divide Control Register
11Aug98@14:48h Intermediate Version
Semiconductor Group
23
1998-08
C163-L
DP0L
b
F100
H
E
80
H
P0L Direction Control Register
00
H
DP0H
b
F102
H
E
81
H
P0H Direction Control Register
00
H
DP1L
b
F104
H
E
82
H
P1L Direction Control Register
00
H
DP1H
b
F106
H
E
83
H
P1H Direction Control Register
00
H
DP2
b
FFC2
H
E1
H
Port 2 Direction Control Register
0000
H
DP3
b
FFC6
H
E3
H
Port 3 Direction Control Register
0000
H
DP4
b
FFCA
H
b
FFCE
H
FE00
H
FE02
H
FE04
H
FE06
H
b
F1C0
H
E
E0
H
b
FF0E
H
FE0C
H
FE0E
H
b
F1C2
H
E
E1
H
b
F1C6
H
E
E3
H
b
F1CE
H
E
E7
H
FF1E
H
b
FF00
H
b
FF02
H
b
FF04
H
b
FF06
H
b
FFC0
H
b
FFC4
H
b
FFC8
H
b
FFA2
H
E5
H
E7
H
00
H
01
H
02
H
03
H
Port 4 Direction Control Register
00
H
00
H
0000
H
0001
H
0002
H
0003
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
00
H
FFFF
H
00
H
00
H
00
H
00
H
0000
H
0000
H
00
H
XXXX
H
DP6
Port 6 Direction Control Register
DPP0
CPU Data Page Pointer 0 Register (10 bits)
DPP1
CPU Data Page Pointer 1 Register (10 bits)
DPP2
CPU Data Page Pointer 2 Register (10 bits)
DPP3
CPU Data Page Pointer 3 Register (10 bits)
EXICON
External Interrupt Control Register
MDC
87
H
06
H
07
H
MDH
CPU Multiply Divide Register – High Word
MDL
CPU Multiply Divide Register – Low Word
ODP2
Port 2 Open Drain Control Register
ODP3
Port 3 Open Drain Control Register
ODP6
Port 6 Open Drain Control Register
ONES
8F
H
80
H
81
H
82
H
83
H
E0
H
E2
H
E4
H
D1
H
Constant Value 1’s Register (read only)
P0L
Port 0 Low Register (Lower half of PORT0)
P0H
Port 0 High Register (Upper half of PORT0)
P1L
Port 1 Low Register (Lower half of PORT1)
P1H
Port 1 High Register (Upper half of PORT1)
P2
Port 2 Register
P3
Port 3 Register
P4
Port 4 Register (8 bits)
P5
Port 5 Register (read only)
Special Function Registers Overview
(cont’d)
Name
Physical
Address
8-Bit
Address
Description
Reset
Value