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11Aug98@14:48h Intermediate Version
Semiconductor Group
5
1998-08
C163-L
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
23
24
25
26
29
30
31
32
IO
O
O
O
O
O
O
O
O
O
IO
O
O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output via direction bits. For a pin configured as input, the
output driver is put into high-impedance state.
In case of an external bus configuration, Port 4 can be used to output
the segment address lines and it provides the SSP interface lines:
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line,
SSPCE1
SSP Chip Enable Line 1
A21
Segment Address Line,
SSPCE0
SSP Chip Enable Line 0
A22
Segment Address Line,
SSPDAT
SSP Data Input/Output Line
A23
Most Significant Segment Addr. Line
SSPCLK
SSP Clock Output Line
RD
33
O
External Memory Read Strobe. RD is activated for every external
instruction or data read access.
WR/
WRL
34
O
External Memory Write Strobe. In WR-mode this pin is activated for
every external data write access. In WRL-mode this pin is activated for
low byte data write accesses on a 16-bit bus, and for every data write
access on an 8-bit bus. See bit WRCFG in register SYSCON for mode
selection.
READY
35
I
Ready Input. When the Ready function is enabled, a high level at this
pin during an external memory access will force the insertion of memory
cycle time waitstates until the pin returns to a low level.
ALE
36
O
Address Latch Enable Output. Can be used for latching the address
into external memory or an address latch in the multiplexed bus modes.
EA
37
I
External Access Enable pin. A low level at this pin during and after
Reset forces the C163-L to begin instruction execution out of external
memory. A high level forces execution out of the internal ROM. The
C163-L must have this pin tied to ‘0’.
Pin Definitions and Functions
(cont’d)
Symbol Pin
Numb.
TQFP
Input
Out-
put
Function