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GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 Ext.Up/Down Ctrl.Input
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
11Aug98@14:48h Intermediate Version
Semiconductor Group
4
1998-08
C163-L
Pin Definitions and Functions
Symbol Pin
Numb.
TQFP
Input
Out-
put
Function
P5
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
98
99
100
1
2
3
I
I
I
I
I
I
I
Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The
pins of Port 5 also serve as timer inputs:
T6EUD
GPT2 Timer T6 External Up/Down Control Input
T5EUD
GPT2 Timer T5 External Up/Down Control Input
T6IN
GPT2 Timer T6 Count Input
T5IN
GPT2 Timer T5 Count Input
T4EUD
GPT1 Timer T4 External Up/Down Control Input
T2EUD
GPT1 Timer T2 External Up/Down Control Input
XTAL1
XTAL2
5
6
I
O
Input to the oscillator amplifier and input to the internal clock generator.
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while leaving
XTAL2 unconnected. Minimum and maximum high/low and rise/fall
times specified in the AC Characteristics must be observed.
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
IO
O
I
O
I
I
I
I
O
IO
O
O
O
Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin configured
as input, the output driver is put into high-impedance state. Port 3
outputs can be configured as push/pull or open drain drivers.
Some Port 3 pins also serve for alternate functions:
-
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
T3IN
T2IN
-
-
T
×
D0
R
×
D0
BHE
WRH
-
CLKOUT
ASC0 Clock/Data Output (Asyn./Syn.)
ASC0 Data Input (Asyn.) or I/O (Syn.)
Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe
System Clock Output (=CPU Clock)