參數(shù)資料
型號： C163-L
廠商： SIEMENS AG
英文描述： 16-bit CMOS Single-Chip Microcontroller
中文描述： 16位CMOS單片機(jī)
文件頁數(shù)： 43/68頁
文件大?。?/td> 625K
代理商： C163-L
11Aug98@14:48h Intermediate Version
Semiconductor Group
41
1998-08
C163-L
AC Characteristics
Multiplexed Bus
(Reduced Supply Voltage Range)
(Operating Conditions apply,
C
L
= 100 pF)
ALE cycle time = 6 TCL + 2
t
A
+
t
C
+
t
F
(250 ns at 12 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 12 MHz
Variable CPU Clock
1 / 2TCL = 1 to 12 MHz
Unit
min.
max.
min.
TCL - 20 +
t
A
TCL - 30 +
t
A
TCL - 10 +
t
A
TCL - 10 +
t
A
max.
ALE high time
t
5
t
6
t
7
t
8
CC 22 +
t
A
CC 12 +
t
A
CC 32 +
t
A
CC 32 +
t
A
–
–
ns
Address setup to ALE
–
–
ns
Address hold after ALE
–
–
ns
ALE falling edge to RD,
WR (with RW-delay)
–
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC -10 +
t
A
–
-10 +
t
A
–
ns
Address float after RD, WR
(with RW-delay)
t
10
CC –
6
–
6
ns
Address float after RD, WR
(no RW-delay)
t
11
CC –
48
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t
12
CC 63 +
t
C
–
2TCL - 20
+
t
C
3TCL - 20
+
t
C
–
–
ns
RD, WR low time
(no RW-delay)
t
13
CC 105 +
t
C
–
–
ns
RD to valid data in
(with RW-delay)
t
14
SR –
49 +
t
C
2TCL - 34
+
t
C
3TCL - 34
+
t
C
3TCL - 32
+
t
A
+
t
C
4TCL - 52
+
2
t
A
+
t
C
–
ns
RD to valid data in
(no RW-delay)
t
15
SR –
91 +
t
C
–
ns
ALE low to valid data in
t
16
SR –
93
+
t
A
+
t
C
115
+
2
t
A
+
t
C
–
–
ns
Address to valid data in
t
17
SR –
–
ns
Data hold after RD
rising edge
t
18
SR 0
0
ns
Data float after RD
t
19
t
22
SR –
CC 47 +
t
C
69 +
t
F
–
–
2TCL - 14 +
t
F
ns
–
Data valid to WR
2TCL - 36
+
t
C
2TCL - 14
+
t
F
2TCL - 14
+
t
F
ns
Data hold after WR
t
23
CC 69 +
t
F
–
–
ns
ALE rising edge after RD,
WR
t
25
CC 69 +
t
F
–
–
ns
相關(guān)PDF資料
PDF描述
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