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參數(shù)資料
| 型號(hào)： | C5NPD0-DS |
| 英文描述： | QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS |
| 中文描述： | 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0 |
| 文件頁(yè)數(shù)： | 42/100頁(yè) |
| 文件大?。?/td> | 2163K |
| 代理商： | C5NPD0-DS |
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42
CHAPTER 2: SIGNAL DESCRIPTIONS
C5NPD0-DS/D REV 04
MOTOROLA GENERAL BUSINESS INFORMATION
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
Figure 4
PROM Interface Diagram
The PROM interface operates in the following manner:
Two accesses are piplined together to execute one 32-bit fetch. The steps are shown in
Figure 5
.
1
The PROM_ADDR is loaded into the network processor internal shift register.
2
The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3
SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register.
4
SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit
PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift
register.
5
SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register and the first PROM_DATA into the external shift register.
6
SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network
processor internal shift register.
External Logic
PROM_ADDR<21:1>
15
15
16
PROM _LO_Word
PROM _H_Word
C-5 Network Processor
PROM Clock Gen.
31
21
21
6
1
PROM _Return_Data
PROM Sequencer
21
0
CE
0
SPCLK
SPLD
SPDO
SPDI
Internal Shift
Register
PROM_ADDR<21:1>
CE
21
6 0
21
0
21
1
PROMPROM_Data
16
External Shift Register
F
n
.
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