參數(shù)資料
型號(hào): C5NPD0-DS
英文描述: QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述: 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁(yè)數(shù): 89/100頁(yè)
文件大?。?/td> 2163K
代理商: C5NPD0-DS
AC Timing Specifications
89
MOTOROLA GENERAL BUSINESS INFORMATION
C5NPD0-DS/D REV 04
QMU Timing
Specifications
The QMU timing specifications are shown in
Figure 25
and described in
Table 55
.
Figure 25
QMU Timing Diagram
Data (TDn)
TD0 - TD63
Table 54
Signal Groups in TLU Timing Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
QCLK
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
QCMDn
(output)
QDATAn
(output)
QDATAn
(input)
T
qc
T
qdo
T
qdv
T
qdz
T
qds
T
qdh
T
qco
Table 55
QMU Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
COMMENT
Tqc
QMU Cycle Time
2 x Tsc
4 x Tsc
ns
ns
1X Clock Mode
2X Clock Mode
Tqco
QMU Ctrl Output
1.5
1/2 Tsc + 1.0
Tsc + 1.0
ns
1X Clock Mode
2X Clock Mode
Tqds
QMU Data Setup
3.1
ns
Tqdh
QMU Data Hold
1.3
3.5
ns
Tqdo
QMU Data Output
1.5
1/2 Tsc + 1.0
Tsc + 1.0
ns
1X Clock Mode
2X Clock Mode
Tqdz
QMU Data Clk to Tri*
1.1
5.5
ns
F
n
.
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