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參數(shù)資料
| 型號(hào)： | CDB4351 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 14/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS4351 DAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Popguard® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -10°C ~ 70°C |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | CS4351 |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS4351-DZZ-ND - IC DAC STER 112DB 192KHZ 20TSSOP 598-1055-5-ND - IC DAC STER 112DB 192KHZ 20TSSOP |
| 其它名稱： | 598-1152 |
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DS566F1
21
CS4351
4.9.2.2
IC Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifica-
tions.
1. Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be
100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see Section 4.10.2) if an IC read is the first operation performed on
the device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read,
then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary to
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the
IC Write instructions followed by step 1 of the IC Read section. If no further reads from other reg-
isters are desired, initiate a STOP condition to the bus.
4.9.3
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 10 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
4.9.3.1
SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in Section 8.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
SD A
SCL
100110
AD0
R/W
Start
ACK
DAT A
1-8
ACK
DA TA
1-8
ACK
Stop
NOTE
NOTE: If operation is a write, this byte contains the M em ory Address Pointer, M AP. If
operation is a read, this byte contains the data of the register pointed to by the M AP.
Figure 9. Control Port Timing, IC Mode
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