參數(shù)資料
型號: CMOD232+
廠商: Maxim Integrated Products
文件頁數(shù): 10/36頁
文件大小: 0K
描述: EVAL SYSTEM FOR MAX9850
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
18
______________________________________________________________________________________
*The first frequency listed is the minimum MCLK frequency required to operate in integer mode. The range of frequencies indicates
the MCLK frequencies the MAX9850 needs to operate in any mode.
Table 5. Acceptable MCLK Frequency Ranges
MINIMUM ICLK
(MHz)
MAXIMUM ICLK
(MHz)
ACCEPTABLE MCLK FREQUENCIES*
(MHz)
LRCLK
(kHz)
INTEGER MODE
(160 x fLRCLK)
NONINTEGER
MODE
(176 x fLRCLK)
ANY MODE
IC(1:0) = 0x0
SF = 1
IC(1:0) = 0x1
SF = 2
IC(1:0) = 0x2
SF = 3
IC(1:0) = 0x3
SF = 4
8
1.280
1.4080
13.0
1.280 and
1.4080 to 13.0
2.560 and
2.8160 to 26.0
3.840 and
4.2240 to 39.0
5.120 and
5.6320 to 40.0
11.025
1.764
1.9404
13.0
1.764 and
1.9404 to 13.0
3.528 and
3.8808 to 26.0
5.292 and
5.8212 to 39.0
7.056 and
7.7616 to 40.0
12
1.920
2.1120
13.0
1.920 and
2.1120 to 13.0
3.840 and
4.2240 to 26.0
5.760 and
6.3360 to 39.0
7.680 and
8.4480 to 40.0
16
2.560
2.8160
13.0
2.560 and
2.8160 to 13.0
5.120 and
5.6320 to 26.0
7.680 and
8.4480 to 39.0
10.240 and
11.2640 to 40.0
22.05
3.528
3.8808
13.0
3.528 and
3.8808 to 13.0
7.056 and
7.7616 to 26.0
10.584 and
11.6424 to 39.0
14.112 and
15.5232 to 40.0
24
3.840
4.2240
13.0
3.840 and
4.2240 to 13.0
7.680 and
8.4480 to 26.0
11.520 and
12.6720 to 39.0
15.360 and
16.8960 to 40.0
32
5.120
5.6320
13.0
5.120 and
5.6320 to 13.0
10.240 and
11.2640 to 26.0
15.360 and
16.8960 to 39.0
20.480 and
22.5280 to 40.0
44.1
7.056
7.7616
13.0
7.056 and
7.7616 to 13.0
14.112 and
15.5232 to 26.0
21.168 and
23.2848 to 39.0
28.224 and
31.0464 to 40.0
48
7.680
8.4480
13.0
7.680 and
8.4480 to 13.0
15.360 and
16.8960 to 26.0
23.040 and
25.3440 to 39.0
30.720 and
33.7920 to 40.0
SLAVE MODE
(MAS = 0)
MASTER MODE
(MAS = 1)
MODE
LRCLK and BCLK signals supplied
from external source
LRCLK and BCLK signals supplied
by MAX9850
NONINTEGER
MODE (INT = 0)
LRCLK may be any frequency
within an acceptable range
Asynchronous
INTEGER MODE
(INT = 1)
ICLK and LRCLK must be
synchronous and exact integer
ratio related
Synchronous
Table 6. DAC Operating Modes
NMSB LSB
,
= 0
N
f
MSB LSB
LRCLK
ICLK
,
=
×
2
22
N
f
N
LSB
ICLK
LRCLK
MSB
=
×
=
16
0
,
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