參數(shù)資料
型號: CMOD232+
廠商: Maxim Integrated Products
文件頁數(shù): 33/36頁
文件大?。?/td> 0K
描述: EVAL SYSTEM FOR MAX9850
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F to AGND,
RLOAD_HP = 32
Ω to AGND, RLOAD_LINE = 10kΩ to AGND, fLRCLK = 48kHz, fMCLK = 12.288MHz, volume set to -9.5dB, TA = TMIN to
TMAX, unless otherwise noted. Typical specifications at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
2C TIMING
Serial Clock Frequency
fSCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
0.6
s
SCL Pulse-Width Low
tLOW
1.3
s
SCL Pulse-Width High
tHIGH
0.6
s
Repeated START Condition
Setup Time
tSU, STA
0.6
s
Data Hold Time
tHD, DAT
0
900
ns
Data Setup Time
tSU, DAT
100
ns
Bus Capacitance
CB
400
pF
SDA and SCL Receiving Rise
Time (Note 8)
tR
20 +
0.1CB
300
ns
SDA and SCL Receiving Fall
Time (Note 8)
tF
20 +
0.1CB
300
ns
DVDD = 1.8V, TA = +25°C
20 +
0.1CB
250
SDA Transmitting Fall Time
(Note 8)
tF
DVDD = 3.6V, TA = +25°C
20 +
0.05CB
250
ns
Setup Time for STOP Condition
tSU, STO
0.6
s
Pulse Width of Suppressed Spike
tSP
050
ns
DIGITAL AUDIO TIMING
BCLK Period (Note 9)
tBCLK
3 x
1 / fICLK
ns
Low or High BCLK Pulse Width
tBCLK_PW
0.35 x
tBCLK
ns
BCLK and LRCLK Rise Time
tR
Master mode, CLOAD = 15pF
1
ns
BCLK and LRCLK Fall Time
tF
Master mode, CLOAD = 15pF
1
ns
SDIN or LRCLK to BCLK Rising
Setup Time
tDBSU,
tBWSU
30
ns
DVDD = 1.8V
0
SDIN or LRCLK to BCLK Rising
Hold Time
tDBH,
tBWBH
DVDD = 3.6V
5
ns
Note 1: The MAX9850 is 100% production tested at TA = +25°C and is guaranteed by design for TA = TMIN to TMAX.
Note 2: Full operation is defined as clocking all zeros into the DAC while the DAC, headphone outputs, and line outputs are all enabled.
Note 3: DAC performance specifications measured using the line outputs, OUTL and OUTR.
Note 4: Dynamic range is defined as the SNR of a 1kHz, -60dBFS input signal measured with an A-weighted filter, then normalized
to full scale (+60dB).
相關(guān)PDF資料
PDF描述
562A011-3/86-0 BOOT MOLDED
0210391020 CABLE JUMPER 1MM .178M 31POS
TCSD-10-D-04.50-01-N-R CABLE STRIPS - SEE NOTES
0982660809 CBL 10POS 0.5MM JMPR TYPE A 1'
VI-J4Z-EX CONVERTER MOD DC/DC 2V 30W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CMOD232+ 功能描述:界面開發(fā)工具 Cmod232+ Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
CMOD3003 功能描述:二極管 - 通用,功率,開關(guān) ULTRAMINI SURFACE MOUNT RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Switching Diodes 峰值反向電壓:600 V 正向連續(xù)電流:200 A 最大浪涌電流:800 A 配置: 恢復時間:2000 ns 正向電壓下降:1.25 V 最大反向漏泄電流:300 uA 最大功率耗散: 工作溫度范圍: 安裝風格:SMD/SMT 封裝 / 箱體:ISOTOP 封裝:Tube
CMOD3003 BK 制造商:Central Semiconductor Corp 功能描述:Diode Switching 180V 0.6A Box
CMOD3003 TR 制造商:Central Semiconductor Corp 功能描述:Diodes - General Purpose, Power, Switching ULTRAMINI SURFACE MOUNT
CMOD3003_10 制造商:CENTRAL 制造商全稱:Central Semiconductor Corp 功能描述:SURFACE MOUNT LOW LEAKAGE SILICON SWITCHING DIODE