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參數(shù)資料
| 型號： | CMOD232+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL SYSTEM FOR MAX9850 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Slew-Rate Control (SR(1:0))
00 = Headphone volume slews from code 0x00 to 0x28
in 63s. Not recommended when ZDEN = 1.
01 = Headphone volume slews from code 0x00 to 0x28
in 125ms.
10 = Headphone volume slews from code 0x00 to 0x28
in 63ms.
11 = Headphone volume slews from code 0x00 to 0x28
in 42ms.
Program SR(1:0) to set the rate that the MAX9850 uses to
slew between two volume settings. The slew-rate control
also controls the amount of time the headphone outputs
take to mute or shut down after the command is given.
Charge-Pump Clock Divider (CP(4:0))
CP(4:0) controls the charge-pump clock divider. The
charge-pump clock frequency (fCPCLK) is derived from
either ICLK or from the internal oscillator.
Program CP(4:0) = 0x00 to enable the 667kHz internal
oscillator. This allows the headphone amplifiers and
line outputs to operate when the DAC is disabled.
Programming CP(4:0) to any value other than 0x00 dis-
ables the internal oscillator and derives the charge-
pump clock from ICLK. Program CP(4:0) with a value
that creates a 667kHz
±20% charge-pump clock from
ICLK by the following equation:
where:
fMCLK = MCLK frequency.
NCP(4:0) = decimal value of CP(4:0). NCP(4:0) must be
greater than 1 when deriving the charge-pump clock
from ICLK.
fCP = charge-pump clock frequency. Program fCP =
667kHz
±20% for proper operation.
SF = MCLK scale factor. SF is the decimal value of
IC(1:0) + 1.
LRCLK MSB and LRCLK LSB Registers
Integer Mode (INT)
1 = Configure the MAX9850 to integer mode.
0 = Configure the MAX9850 to noninteger mode.
Integer mode operation requires that ICLK is an integer
multiple of 16 times the sample rate (fLRCLK). See the
DAC Operating Modes section. When in integer mode,
fLRCLK = fICLK / (16 x LSB(7:0)).
LRCLK MSB Divider (MSB(14:8))
MSB(14:8) and LSB(7:0) are used to determine fLRCLK
when in noninteger mode only (see the DAC Operating
Modes section). For noninteger mode:
LRCLK LSB Divider (LSB(7:0))
LSB(7:0) combined with MSB(14:8) sets the LRCLK
divider when the MAX9850 is configured in noninteger
mode. Only LSB(7:0) is used to determine fLRCLK when
the MAX9850 is configured in integer mode. See the
DAC Operating Modes section.
Digital Audio Register
Master Mode (MAS)
1 = Configure the MAX9850 to master mode.
0 = Configure the MAX9850 to slave mode.
Set MAS = 1 to configure the MAX9850 to master mode.
The LRCLK and BCLK are generated by the MAX9850
when in master mode. Set MAS = 0 to configure the
MAX9850 as a digital audio slave that accepts LRCLK
and BCLK from an external digital audio source.
LRCLK Invert (INV)
1 = Left audio data is clocked in when LRCLK is high
and right data is clocked in when LRCLK is low.
0 = Left audio data is clocked in when LRCLK is low
and right data is clocked in when LRCLK is high.
Set INV = 0 to conform to the I2S standard.
Bit Clock Invert (BCINV)
1 = Digital data at SDIN latches in on the falling edge of
BCLK.
0 = Digital data at SDIN latches in on the rising edge of
BCLK.
Set BCINV = 0 to conform to the I2S standard.
N
f
MSB LSB
LRCLK
ICLK
,
=
×
2
22
f
SF
CP
MCLK
NCP
=
××
2
40
(: )
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________
27
Table 19. LRCLK MSB (0x8) and LRCLK
LSB (0x9) Read/Write, Bit Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
INT
MSB(14:8)
LSB(7:0)
Table 20. Digital Audio (0xA) Read/Write,
Bit Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
MAS
INV
BCINV
LSF
DLY
RTJ
WS(1:0)
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